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![Stephen Warren](/assets/img/avatar_default.png)
The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
201 lines
3.8 KiB
C
201 lines
3.8 KiB
C
/*
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* Copyright (C) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
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{
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return (struct clk_ops *)dev->driver->ops;
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}
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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#ifdef CONFIG_SPL_BUILD
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int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
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{
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int ret;
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u32 cell[2];
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if (index != 0)
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return -ENOSYS;
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assert(clk);
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ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
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if (ret)
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return ret;
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ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
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cell, 2);
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if (ret)
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return ret;
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clk->id = cell[1];
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return 0;
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}
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int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
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{
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return -ENOSYS;
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}
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#else
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static int clk_of_xlate_default(struct clk *clk,
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struct fdtdec_phandle_args *args)
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{
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debug("%s(clk=%p)\n", __func__, clk);
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if (args->args_count > 1) {
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debug("Invaild args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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if (args->args_count)
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clk->id = args->args[0];
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else
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clk->id = 0;
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return 0;
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}
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int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
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{
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int ret;
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struct fdtdec_phandle_args args;
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struct udevice *dev_clk;
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struct clk_ops *ops;
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debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
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assert(clk);
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ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
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"clocks", "#clock-cells", 0, index,
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&args);
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if (ret) {
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debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
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__func__, ret);
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return ret;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev_clk);
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if (ret) {
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debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
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__func__, ret);
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return ret;
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}
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ops = clk_dev_ops(dev_clk);
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if (ops->of_xlate)
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ret = ops->of_xlate(clk, &args);
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else
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ret = clk_of_xlate_default(clk, &args);
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if (ret) {
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debug("of_xlate() failed: %d\n", ret);
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return ret;
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}
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return clk_request(dev_clk, clk);
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}
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int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
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{
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int index;
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debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
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index = fdt_find_string(gd->fdt_blob, dev->of_offset, "clock-names",
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name);
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if (index < 0) {
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debug("fdt_find_string() failed: %d\n", index);
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return index;
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}
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return clk_get_by_index(dev, index, clk);
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}
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#endif
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#endif
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int clk_request(struct udevice *dev, struct clk *clk)
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{
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struct clk_ops *ops = clk_dev_ops(dev);
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debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
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clk->dev = dev;
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if (!ops->request)
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return 0;
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return ops->request(clk);
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}
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int clk_free(struct clk *clk)
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{
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struct clk_ops *ops = clk_dev_ops(clk->dev);
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debug("%s(clk=%p)\n", __func__, clk);
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if (!ops->free)
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return 0;
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return ops->free(clk);
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}
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ulong clk_get_rate(struct clk *clk)
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{
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struct clk_ops *ops = clk_dev_ops(clk->dev);
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debug("%s(clk=%p)\n", __func__, clk);
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if (!ops->get_rate)
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return -ENOSYS;
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return ops->get_rate(clk);
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}
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ulong clk_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_ops *ops = clk_dev_ops(clk->dev);
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debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
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if (!ops->set_rate)
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return -ENOSYS;
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return ops->set_rate(clk, rate);
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}
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int clk_enable(struct clk *clk)
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{
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struct clk_ops *ops = clk_dev_ops(clk->dev);
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debug("%s(clk=%p)\n", __func__, clk);
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if (!ops->enable)
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return -ENOSYS;
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return ops->enable(clk);
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}
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int clk_disable(struct clk *clk)
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{
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struct clk_ops *ops = clk_dev_ops(clk->dev);
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debug("%s(clk=%p)\n", __func__, clk);
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if (!ops->disable)
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return -ENOSYS;
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return ops->disable(clk);
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}
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UCLASS_DRIVER(clk) = {
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.id = UCLASS_CLK,
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.name = "clk",
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};
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