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![Roy Zang](/assets/img/avatar_default.png)
The P1023RDS board is the reference board for the P1023 SoC. Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe, UART, I2C, etc. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
102 lines
2.7 KiB
Plaintext
102 lines
2.7 KiB
Plaintext
Overview
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--------
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The P1023 process includes a performance optimized implementation of the
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QorIQ data Path Acceleration Architecture (DPAA). This architecture
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provides the infrastructure to support simplified sharing of networking
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interfaces and accelerators by multiple CPU cores. P1023 is an e500 based
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dual core SOC.
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P1023RDS board is a Low End Dual core platform supporting the P1023
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processor of QorIQ series.
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Building U-boot
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---------------
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To build the u-boot for P1023RDS:
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Configure to NOR boot:
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make P1023RDS_config
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Configure to NAND boot:
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make P1023RDS_NAND_config
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Build:
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make
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Board Switches
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--------------
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Most switches on the board should not be changed. The most frequent
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user-settable switches on the board are used to configure
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the flash banks.
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J4: all open
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Default NOR flash boot switch setting:
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Sw3[1:8]: off on on off on on off off
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Sw4[1:8]: off off off on off off off off
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Sw6[1:8]: off on off on off on on off
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Sw7[1:8]: off on off off on off off off
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Sw8[1:8]: on off off off off off off off
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For NAND flash boot,set
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Sw4[1:4]: off on on on
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The default native ethernet setting is for RGMII mode.
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To use SGMII mode, set
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SW8[1:2]: OFF OFF
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SW7[6:7]: ON ON
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Memory Map
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----------
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0x0000_0000 0x7fff_ffff DDR 2G Cacheable
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0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
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0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
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0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
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0xe000_0000 0xe003_ffff BCSR 256K BCSR
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0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
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0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
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0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
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0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable
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0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
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Flashing u-boot Images
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---------------
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To program the image in the boot flash bank:
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NOR flash boot:
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=> tftp 1000000 u-boot.bin
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=> protect off all
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=> erase eff80000 efffffff
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=> cp.b 1000000 eff80000 80000
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NAND flash boot:
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=> tftp 1000000 u-boot-nand.bin
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=> nand erase 0 80000
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=> nand write 1000000 0 80000
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Firmware ucode location
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---------------------------------
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Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work.
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u-boot loads ucode FLASH. The location for ucode:
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NOR Flash: 0xfe000000
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NAND Flash: 0x1f00000
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Using the Device Tree Source File
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---------------------------------
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To create the DTB (Device Tree Binary) image file,
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use a command similar to this:
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dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb
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Likely, that .dts file will come from here;
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linux-2.6/arch/powerpc/boot/dts/p1023rds.dts
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or
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make p1023rds.dtb ARCH=powerpc
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in linux-2.6 directory.
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Booting Linux
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-------------
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Place a linux uImage in the TFTP disk area.
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tftp 1000000 uImage
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tftp 2000000 rootfs.ext2.gz.uboot
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tftp c00000 p1023rds.dtb
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bootm 1000000 2000000 c00000
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