mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 12:46:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010, 2011
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _WARMBOOT_AVP_H_
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#define _WARMBOOT_AVP_H_
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#define TEGRA_DEV_L 0
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#define TEGRA_DEV_H 1
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#define TEGRA_DEV_U 2
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#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
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#define SIMPLE_PLLE (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE)
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#define TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0)
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#define TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4)
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#define USEC_CFG_DIVISOR_MASK 0xffff
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#define CONFIG_CTL_TBE (1 << 7)
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#define CONFIG_CTL_JTAG (1 << 6)
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#define CPU_RST (1 << 0)
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#define CLK_ENB_CPU (1 << 0)
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#define SWR_TRIG_SYS_RST (1 << 2)
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#define SWR_CSITE_RST (1 << 9)
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#define PWRGATE_STATUS_CPU (1 << 0)
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#define PWRGATE_TOGGLE_PARTID_CPU (0 << 0)
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#define PWRGATE_TOGGLE_START (1 << 8)
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#define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 (3 << 0)
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#define CPU_CMPLX_CPU0_CLK_STP_STOP (1 << 8)
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#define CPU_CMPLX_CPU0_CLK_STP_RUN (0 << 8)
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#define CPU_CMPLX_CPU1_CLK_STP_STOP (1 << 9)
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#define CPU_CMPLX_CPU1_CLK_STP_RUN (0 << 9)
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#define CPU_CMPLX_CPURESET0 (1 << 0)
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#define CPU_CMPLX_CPURESET1 (1 << 1)
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#define CPU_CMPLX_DERESET0 (1 << 4)
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#define CPU_CMPLX_DERESET1 (1 << 5)
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#define CPU_CMPLX_DBGRESET0 (1 << 12)
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#define CPU_CMPLX_DBGRESET1 (1 << 13)
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#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0)
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#define PLLM_OUT1_CLKEN_ENABLE (1 << 1)
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#define PLLM_OUT1_RATIO_VAL_8 (8 << 8)
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#define SCLK_SYS_STATE_IDLE (1 << 28)
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#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
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#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
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#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
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#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
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#define EVENT_ZERO_VAL_20 (20 << 0)
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#define EVENT_MSEC (1 << 24)
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#define EVENT_JTAG (1 << 28)
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#define EVENT_MODE_STOP (2 << 29)
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#define CCLK_PLLP_BURST_POLICY 0x20004444
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#endif
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