mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-10 23:03:29 +09:00
5e239183f6
At present these two sections of code are linked together into a single 2KB chunk in a single file. Some Intel SoCs like to have a FIT (Firmware Interface Table) in the ROM and the pointer for this needs to go at 0xffffffc0 which is in the middle of these two sections. Make use of the new 'reset' entry and change the existing 16-bit entry to include just the 16-bit data. Signed-off-by: Simon Glass <sjg@chromium.org>
143 lines
2.5 KiB
Plaintext
143 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <config.h>
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#ifdef CONFIG_CHROMEOS
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/ {
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binman {
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multiple-images;
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rom: rom {
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};
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};
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};
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#else
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/ {
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rom: binman {
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};
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};
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#endif
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#ifdef CONFIG_ROM_SIZE
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&rom {
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filename = "u-boot.rom";
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end-at-4gb;
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sort-by-offset;
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pad-byte = <0xff>;
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size = <CONFIG_ROM_SIZE>;
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#ifdef CONFIG_HAVE_INTEL_ME
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intel-descriptor {
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filename = CONFIG_FLASH_DESCRIPTOR_FILE;
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};
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intel-me {
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filename = CONFIG_INTEL_ME_FILE;
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};
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#endif
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#ifdef CONFIG_TPL
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u-boot-tpl-with-ucode-ptr {
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offset = <CONFIG_TPL_TEXT_BASE>;
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};
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u-boot-tpl-dtb {
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};
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u-boot-spl {
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offset = <CONFIG_SPL_TEXT_BASE>;
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};
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u-boot-spl-dtb {
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};
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u-boot {
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offset = <CONFIG_SYS_TEXT_BASE>;
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};
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#elif defined(CONFIG_SPL)
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u-boot-spl-with-ucode-ptr {
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offset = <CONFIG_SPL_TEXT_BASE>;
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};
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u-boot-dtb-with-ucode2 {
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type = "u-boot-dtb-with-ucode";
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};
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u-boot {
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/*
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* TODO(sjg@chromium.org):
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* Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
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* for boards with textbase in SDRAM we cannot do this. Just use
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* an assumed-valid value (1MB before the end of flash) here so
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* that we can actually build an image for coreboot, etc.
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* We need a better solution, perhaps a separate Kconfig.
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*/
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#if CONFIG_SYS_TEXT_BASE == 0x1110000
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offset = <0xfff00000>;
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#else
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offset = <CONFIG_SYS_TEXT_BASE>;
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#endif
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};
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#else
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u-boot-with-ucode-ptr {
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offset = <CONFIG_SYS_TEXT_BASE>;
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};
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#endif
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u-boot-dtb-with-ucode {
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};
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u-boot-ucode {
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align = <16>;
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};
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#ifdef CONFIG_HAVE_MRC
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intel-mrc {
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offset = <CONFIG_X86_MRC_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_FSP
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intel-fsp {
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filename = CONFIG_FSP_FILE;
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offset = <CONFIG_FSP_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_CMC
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intel-cmc {
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filename = CONFIG_CMC_FILE;
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offset = <CONFIG_CMC_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_VGA_BIOS
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intel-vga {
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filename = CONFIG_VGA_BIOS_FILE;
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offset = <CONFIG_VGA_BIOS_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_VBT
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intel-vbt {
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filename = CONFIG_VBT_FILE;
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offset = <CONFIG_VBT_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_REFCODE
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intel-refcode {
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offset = <CONFIG_X86_REFCODE_ADDR>;
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};
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#endif
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#ifdef CONFIG_TPL
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x86-start16-tpl {
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offset = <CONFIG_SYS_X86_START16>;
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};
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x86-reset16-tpl {
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offset = <CONFIG_RESET_VEC_LOC>;
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};
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#elif defined(CONFIG_SPL)
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x86-start16-spl {
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offset = <CONFIG_SYS_X86_START16>;
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};
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x86-reset16-spl {
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offset = <CONFIG_RESET_VEC_LOC>;
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};
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#else
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x86-start16 {
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offset = <CONFIG_SYS_X86_START16>;
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};
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x86-reset16 {
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offset = <CONFIG_RESET_VEC_LOC>;
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};
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#endif
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};
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#endif
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