mirror of
https://github.com/brain-hackers/u-boot-brain
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7e44f2b710
Previously, SPD configuration of RAM was non functional on this board. Now that the root cause is known (an i2c address conflict), there is a simple end-user workaround - remove the old slower local bus 128MB module and then SPD detection on the main DDR2 memory module works fine. We make the enablement of the LBC SDRAM support conditional on being not SPD enabled. We can revisit this dependency as the hardware workaround becomes available. Turning off LBC SDRAM support revealed a couple implict dependencies in the tlb/law code that always expected an LBC SDRAM address. This has been tested with the default 256MB module, a 512MB a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration worked fine in all cases. The default configuration remains to go with the hard coded DDR config, so the default build will continue to work on boards where people don't bother to read the docs. But the advantage of going to the SPD config is that even the small default module gets configured for CL3 instead of CL4. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
139 lines
4.1 KiB
C
139 lines
4.1 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/*
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* TLB 0: 64M Non-cacheable, guarded
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* 0xfc000000 56M unused
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* 0xff800000 8M boot FLASH
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* .... or ....
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* 0xfc000000 64M user flash
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*
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* Out of reset this entry is only 4K.
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*/
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SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 1: 1G Non-cacheable, guarded
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* 0x80000000 512M PCI1 MEM
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* 0xa0000000 512M PCIe MEM
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1G, 1),
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/*
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* TLB 2: 64M Non-cacheable, guarded
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* 0xe0000000 1M CCSRBAR
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* 0xe2000000 8M PCI1 IO
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* 0xe2800000 8M PCIe IO
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_64M, 1),
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#ifdef CONFIG_SYS_LBC_SDRAM_BASE
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/*
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* TLB 3: 64M Cacheable, non-guarded
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* 0xf0000000 64M LBC SDRAM First half
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 3, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 4: 64M Cacheable, non-guarded
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* 0xf4000000 64M LBC SDRAM Second half
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
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CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 4, BOOKE_PAGESZ_64M, 1),
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#endif
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/*
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* TLB 5: 16M Cacheable, non-guarded
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* 0xf8000000 1M 7-segment LED display
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* 0xf8100000 1M User switches
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* 0xf8300000 1M Board revision
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* 0xf8b00000 1M EEPROM
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_16M, 1),
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#ifndef CONFIG_SYS_ALT_BOOT
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/*
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* TLB 6: 64M Non-cacheable, guarded
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* 0xec000000 64M 64MB user FLASH
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_64M, 1),
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#else
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/*
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* TLB 6: 4M Non-cacheable, guarded
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* 0xef800000 4M 1st 1/2 8MB soldered FLASH
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_4M, 1),
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/*
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* TLB 7: 4M Non-cacheable, guarded
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* 0xefc00000 4M 2nd half 8MB soldered FLASH
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
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CONFIG_SYS_ALT_FLASH + 0x400000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 7, BOOKE_PAGESZ_4M, 1),
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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