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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
201 lines
4.6 KiB
C
201 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/systimer.h>
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#include <asm/arch/sysctrl.h>
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#include <asm/arch/wdt.h>
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#include "../drivers/mmc/arm_pl180_mmci.h"
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static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
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static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
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static void flash__init(void);
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static void vexpress_timer_init(void);
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SHOW_BOOT_PROGRESS)
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void show_boot_progress(int progress)
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{
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printf("Boot reached stage %d\n", progress);
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}
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#endif
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static inline void delay(ulong loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b" : "=r" (loops) : "0" (loops));
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
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gd->flags = 0;
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icache_enable();
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flash__init();
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vexpress_timer_init();
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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int cpu_mmc_init(bd_t *bis)
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{
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int rc = 0;
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(void) bis;
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#ifdef CONFIG_ARM_PL180_MMCI
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struct pl180_mmc_host *host;
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struct mmc *mmc;
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host = malloc(sizeof(struct pl180_mmc_host));
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if (!host)
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return -ENOMEM;
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memset(host, 0, sizeof(*host));
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strcpy(host->name, "MMC");
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host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
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host->pwr_init = INIT_PWR;
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host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
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host->voltages = VOLTAGE_WINDOW_MMC;
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host->caps = 0;
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host->clock_in = ARM_MCLK;
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host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
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host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
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rc = arm_pl180_mmci_init(host, &mmc);
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#endif
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return rc;
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}
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static void flash__init(void)
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{
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/* Setup the sytem control register to allow writing to flash */
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writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
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&sysctrl_base->scflashctrl);
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}
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int dram_init(void)
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{
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gd->ram_size =
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get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size =
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get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size =
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get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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return 0;
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}
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/*
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* Start timer:
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* Setup a 32 bit timer, running at 1KHz
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* Versatile Express Motherboard provides 1 MHz timer
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*/
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static void vexpress_timer_init(void)
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{
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/*
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* Set clock frequency in system controller:
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* VEXPRESS_REFCLK is 32KHz
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* VEXPRESS_TIMCLK is 1MHz
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*/
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writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
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SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
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readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
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/*
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* Set Timer0 to be:
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* Enabled, free running, no interrupt, 32-bit, wrapping
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*/
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writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
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writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
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writel(SYSTIMER_EN | SYSTIMER_32BIT |
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readl(&systimer_base->timer0control),
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&systimer_base->timer0control);
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}
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int v2m_cfg_write(u32 devfn, u32 data)
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{
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/* Configuration interface broken? */
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u32 val;
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devfn |= SYS_CFG_START | SYS_CFG_WRITE;
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val = readl(V2M_SYS_CFGSTAT);
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writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
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writel(data, V2M_SYS_CFGDATA);
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writel(devfn, V2M_SYS_CFGCTRL);
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do {
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val = readl(V2M_SYS_CFGSTAT);
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} while (val == 0);
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return !!(val & SYS_CFG_ERR);
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}
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/* Use the ARM Watchdog System to cause reset */
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void reset_cpu(ulong addr)
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{
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if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
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printf("Unable to reboot\n");
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}
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void lowlevel_init(void)
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{
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}
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ulong get_board_rev(void){
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return readl((u32 *)SYS_ID);
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}
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#ifdef CONFIG_ARMV7_NONSEC
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/* Setting the address at which secondary cores start from.
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* Versatile Express uses one address for all cores, so ignore corenr
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*/
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void smp_set_core_boot_addr(unsigned long addr, int corenr)
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{
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/* The SYSFLAGS register on VExpress needs to be cleared first
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* by writing to the next address, since any writes to the address
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* at offset 0 will only be ORed in
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*/
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writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
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writel(addr, CONFIG_SYSFLAGS_ADDR);
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}
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#endif
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