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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
188 lines
6.9 KiB
C
188 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* arch/arm/include/asm/hardware/pci_v3.h
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*
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* Internal header file PCI V3 chip
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*
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* Copyright (C) ARM Limited
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* Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
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*/
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#ifndef ASM_ARM_HARDWARE_PCI_V3_H
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#define ASM_ARM_HARDWARE_PCI_V3_H
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/* -------------------------------------------------------------------------------
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* V3 Local Bus to PCI Bridge definitions
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* -------------------------------------------------------------------------------
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* Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
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* All V3 register names are prefaced by V3_ to avoid clashing with any other
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* PCI definitions. Their names match the user's manual.
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*
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* I'm assuming that I20 is disabled.
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*
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*/
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#define V3_PCI_VENDOR 0x00000000
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#define V3_PCI_DEVICE 0x00000002
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#define V3_PCI_CMD 0x00000004
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#define V3_PCI_STAT 0x00000006
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#define V3_PCI_CC_REV 0x00000008
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#define V3_PCI_HDR_CFG 0x0000000C
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#define V3_PCI_IO_BASE 0x00000010
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#define V3_PCI_BASE0 0x00000014
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#define V3_PCI_BASE1 0x00000018
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#define V3_PCI_SUB_VENDOR 0x0000002C
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#define V3_PCI_SUB_ID 0x0000002E
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#define V3_PCI_ROM 0x00000030
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#define V3_PCI_BPARAM 0x0000003C
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#define V3_PCI_MAP0 0x00000040
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#define V3_PCI_MAP1 0x00000044
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#define V3_PCI_INT_STAT 0x00000048
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#define V3_PCI_INT_CFG 0x0000004C
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#define V3_LB_BASE0 0x00000054
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#define V3_LB_BASE1 0x00000058
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#define V3_LB_MAP0 0x0000005E
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#define V3_LB_MAP1 0x00000062
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#define V3_LB_BASE2 0x00000064
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#define V3_LB_MAP2 0x00000066
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#define V3_LB_SIZE 0x00000068
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#define V3_LB_IO_BASE 0x0000006E
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#define V3_FIFO_CFG 0x00000070
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#define V3_FIFO_PRIORITY 0x00000072
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#define V3_FIFO_STAT 0x00000074
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#define V3_LB_ISTAT 0x00000076
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#define V3_LB_IMASK 0x00000077
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#define V3_SYSTEM 0x00000078
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#define V3_LB_CFG 0x0000007A
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#define V3_PCI_CFG 0x0000007C
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#define V3_DMA_PCI_ADR0 0x00000080
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#define V3_DMA_PCI_ADR1 0x00000090
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#define V3_DMA_LOCAL_ADR0 0x00000084
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#define V3_DMA_LOCAL_ADR1 0x00000094
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#define V3_DMA_LENGTH0 0x00000088
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#define V3_DMA_LENGTH1 0x00000098
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#define V3_DMA_CSR0 0x0000008B
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#define V3_DMA_CSR1 0x0000009B
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#define V3_DMA_CTLB_ADR0 0x0000008C
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#define V3_DMA_CTLB_ADR1 0x0000009C
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#define V3_DMA_DELAY 0x000000E0
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#define V3_MAIL_DATA 0x000000C0
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#define V3_PCI_MAIL_IEWR 0x000000D0
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#define V3_PCI_MAIL_IERD 0x000000D2
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#define V3_LB_MAIL_IEWR 0x000000D4
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#define V3_LB_MAIL_IERD 0x000000D6
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#define V3_MAIL_WR_STAT 0x000000D8
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#define V3_MAIL_RD_STAT 0x000000DA
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#define V3_QBA_MAP 0x000000DC
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/* PCI COMMAND REGISTER bits
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*/
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#define V3_COMMAND_M_FBB_EN (1 << 9)
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#define V3_COMMAND_M_SERR_EN (1 << 8)
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#define V3_COMMAND_M_PAR_EN (1 << 6)
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#define V3_COMMAND_M_MASTER_EN (1 << 2)
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#define V3_COMMAND_M_MEM_EN (1 << 1)
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#define V3_COMMAND_M_IO_EN (1 << 0)
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/* SYSTEM REGISTER bits
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*/
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#define V3_SYSTEM_M_RST_OUT (1 << 15)
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#define V3_SYSTEM_M_LOCK (1 << 14)
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/* PCI_CFG bits
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*/
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#define V3_PCI_CFG_M_I2O_EN (1 << 15)
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#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
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#define V3_PCI_CFG_M_IO_DIS (1 << 13)
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#define V3_PCI_CFG_M_EN3V (1 << 12)
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#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
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#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
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#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
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/* PCI_BASE register bits (PCI -> Local Bus)
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*/
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#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
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#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
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#define V3_PCI_BASE_M_PREFETCH (1 << 3)
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#define V3_PCI_BASE_M_TYPE (3 << 1)
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#define V3_PCI_BASE_M_IO (1 << 0)
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/* PCI MAP register bits (PCI -> Local bus)
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*/
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#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
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#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
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#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
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#define V3_PCI_MAP_M_SWAP (3 << 8)
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#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
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#define V3_PCI_MAP_M_REG_EN (1 << 1)
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#define V3_PCI_MAP_M_ENABLE (1 << 0)
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#define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4)
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#define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4)
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/*
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* LB_BASE0,1 register bits (Local bus -> PCI)
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*/
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#define V3_LB_BASE_ADR_BASE 0xfff00000
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#define V3_LB_BASE_SWAP (3 << 8)
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#define V3_LB_BASE_ADR_SIZE (15 << 4)
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#define V3_LB_BASE_PREFETCH (1 << 3)
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#define V3_LB_BASE_ENABLE (1 << 0)
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#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
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#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
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#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
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#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
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#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
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#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
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#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
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#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
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#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
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#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
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#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
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#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
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#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
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/*
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* LB_MAP0,1 register bits (Local bus -> PCI)
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*/
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#define V3_LB_MAP_MAP_ADR 0xfff0
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#define V3_LB_MAP_TYPE (7 << 1)
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#define V3_LB_MAP_AD_LOW_EN (1 << 0)
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#define V3_LB_MAP_TYPE_IACK (0 << 1)
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#define V3_LB_MAP_TYPE_IO (1 << 1)
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#define V3_LB_MAP_TYPE_MEM (3 << 1)
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#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
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#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
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/* PCI MAP register bits (PCI -> Local bus) */
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#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
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/*
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* LB_BASE2 register bits (Local bus -> PCI IO)
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*/
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#define V3_LB_BASE2_ADR_BASE 0xff00
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#define V3_LB_BASE2_SWAP (3 << 6)
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#define V3_LB_BASE2_ENABLE (1 << 0)
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#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
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/*
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* LB_MAP2 register bits (Local bus -> PCI IO)
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*/
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#define V3_LB_MAP2_MAP_ADR 0xff00
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#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
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#endif
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