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https://github.com/brain-hackers/u-boot-brain
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![York Sun](/assets/img/avatar_default.png)
The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com>
212 lines
4.9 KiB
C
212 lines
4.9 KiB
C
/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/mp.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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void *get_spin_tbl_addr(void)
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{
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return &__spin_table;
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}
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phys_addr_t determine_mp_bootpg(void)
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{
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return (phys_addr_t)&secondary_boot_code;
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}
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int fsl_layerscape_wake_seconday_cores(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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#ifdef CONFIG_FSL_LSCH3
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struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
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#elif defined(CONFIG_FSL_LSCH2)
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struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
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#endif
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u32 cores, cpu_up_mask = 1;
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int i, timeout = 10;
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u64 *table = get_spin_tbl_addr();
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#ifdef COUNTER_FREQUENCY_REAL
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/* update for secondary cores */
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__real_cntfrq = COUNTER_FREQUENCY_REAL;
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flush_dcache_range((unsigned long)&__real_cntfrq,
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(unsigned long)&__real_cntfrq + 8);
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#endif
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cores = cpu_mask();
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/* Clear spin table so that secondary processors
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* observe the correct value after waking up from wfe.
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*/
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memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
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flush_dcache_range((unsigned long)table,
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(unsigned long)table +
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(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
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printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
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#ifdef CONFIG_FSL_LSCH3
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gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
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gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
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gur_out32(&gur->scratchrw[6], 1);
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asm volatile("dsb st" : : : "memory");
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rst->brrl = cores;
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asm volatile("dsb st" : : : "memory");
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#elif defined(CONFIG_FSL_LSCH2)
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scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
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scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
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asm volatile("dsb st" : : : "memory");
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gur_out32(&gur->brrl, cores);
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asm volatile("dsb st" : : : "memory");
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/* Bootup online cores */
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scfg_out32(&scfg->corebcr, cores);
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#endif
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/* This is needed as a precautionary measure.
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* If some code before this has accidentally released the secondary
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* cores then the pre-bootloader code will trap them in a "wfe" unless
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* the scratchrw[6] is set. In this case we need a sev here to get these
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* cores moving again.
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*/
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asm volatile("sev");
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while (timeout--) {
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flush_dcache_range((unsigned long)table, (unsigned long)table +
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CONFIG_MAX_CPUS * 64);
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for (i = 1; i < CONFIG_MAX_CPUS; i++) {
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if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
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SPIN_TABLE_ELEM_STATUS_IDX])
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cpu_up_mask |= 1 << i;
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}
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if (hweight32(cpu_up_mask) == hweight32(cores))
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break;
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udelay(10);
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}
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if (timeout <= 0) {
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printf("Not all cores (0x%x) are up (0x%x)\n",
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cores, cpu_up_mask);
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return 1;
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}
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printf("All (%d) cores are up.\n", hweight32(cores));
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return 0;
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}
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int is_core_valid(unsigned int core)
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{
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return !!((1 << core) & cpu_mask());
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}
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static int is_pos_valid(unsigned int pos)
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{
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return !!((1 << pos) & cpu_pos_mask());
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}
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int is_core_online(u64 cpu_id)
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{
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u64 *table;
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int pos = id_to_core(cpu_id);
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table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
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return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
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}
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int cpu_reset(int nr)
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{
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puts("Feature is not implemented.\n");
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return 0;
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}
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int cpu_disable(int nr)
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{
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puts("Feature is not implemented.\n");
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return 0;
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}
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static int core_to_pos(int nr)
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{
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u32 cores = cpu_pos_mask();
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int i, count = 0;
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if (nr == 0) {
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return 0;
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} else if (nr >= hweight32(cores)) {
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puts("Not a valid core number.\n");
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return -1;
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}
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for (i = 1; i < 32; i++) {
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if (is_pos_valid(i)) {
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count++;
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if (count == nr)
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break;
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}
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}
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if (count != nr)
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return -1;
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return i;
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}
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int cpu_status(int nr)
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{
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u64 *table;
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int pos;
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if (nr == 0) {
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table = (u64 *)get_spin_tbl_addr();
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printf("table base @ 0x%p\n", table);
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} else {
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pos = core_to_pos(nr);
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if (pos < 0)
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return -1;
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table = (u64 *)get_spin_tbl_addr() + pos *
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WORDS_PER_SPIN_TABLE_ENTRY;
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printf("table @ 0x%p\n", table);
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printf(" addr - 0x%016llx\n",
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table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
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printf(" status - 0x%016llx\n",
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table[SPIN_TABLE_ELEM_STATUS_IDX]);
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printf(" lpid - 0x%016llx\n",
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table[SPIN_TABLE_ELEM_LPID_IDX]);
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}
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return 0;
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}
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int cpu_release(int nr, int argc, char * const argv[])
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{
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u64 boot_addr;
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u64 *table = (u64 *)get_spin_tbl_addr();
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int pos;
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pos = core_to_pos(nr);
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if (pos <= 0)
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return -1;
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table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
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boot_addr = simple_strtoull(argv[0], NULL, 16);
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table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
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flush_dcache_range((unsigned long)table,
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(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
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asm volatile("dsb st");
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smp_kick_all_cpus(); /* only those with entry addr set will run */
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/*
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* When the first release command runs, all cores are set to go. Those
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* without a valid entry address will be trapped by "wfe". "sev" kicks
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* them off to check the address again. When set, they continue to run.
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*/
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asm volatile("sev");
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return 0;
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}
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