mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 23:50:26 +09:00
d5dae85f23
Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
110 lines
4.9 KiB
C
110 lines
4.9 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <fpga.h>
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#ifndef _XILINX_H_
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#define _XILINX_H_
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/* Xilinx Model definitions
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*********************************************************************/
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#define CONFIG_SYS_SPARTAN2 CONFIG_SYS_FPGA_DEV( 0x1 )
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#define CONFIG_SYS_VIRTEX_E CONFIG_SYS_FPGA_DEV( 0x2 )
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#define CONFIG_SYS_VIRTEX2 CONFIG_SYS_FPGA_DEV( 0x4 )
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#define CONFIG_SYS_SPARTAN3 CONFIG_SYS_FPGA_DEV( 0x8 )
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#define CONFIG_SYS_ZYNQ CONFIG_SYS_FPGA_DEV(0x10)
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#define CONFIG_SYS_XILINX_SPARTAN2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
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#define CONFIG_SYS_XILINX_VIRTEX_E (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
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#define CONFIG_SYS_XILINX_VIRTEX2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
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#define CONFIG_SYS_XILINX_SPARTAN3 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
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#define CONFIG_SYS_XILINX_ZYNQ (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_ZYNQ)
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/* XXX - Add new models here */
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/* Xilinx Interface definitions
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*********************************************************************/
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#define CONFIG_SYS_XILINX_IF_SS CONFIG_SYS_FPGA_IF( 0x1 ) /* slave serial */
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#define CONFIG_SYS_XILINX_IF_MS CONFIG_SYS_FPGA_IF( 0x2 ) /* master serial */
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#define CONFIG_SYS_XILINX_IF_SP CONFIG_SYS_FPGA_IF( 0x4 ) /* slave parallel */
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#define CONFIG_SYS_XILINX_IF_JTAG CONFIG_SYS_FPGA_IF( 0x8 ) /* jtag */
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#define CONFIG_SYS_XILINX_IF_MSM CONFIG_SYS_FPGA_IF( 0x10 ) /* master selectmap */
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#define CONFIG_SYS_XILINX_IF_SSM CONFIG_SYS_FPGA_IF( 0x20 ) /* slave selectmap */
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/* Xilinx types
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*********************************************************************/
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typedef enum { /* typedef Xilinx_iface */
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min_xilinx_iface_type, /* low range check value */
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slave_serial, /* serial data and external clock */
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master_serial, /* serial data w/ internal clock (not used) */
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slave_parallel, /* parallel data w/ external latch */
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jtag_mode, /* jtag/tap serial (not used ) */
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master_selectmap, /* master SelectMap (virtex2) */
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slave_selectmap, /* slave SelectMap (virtex2) */
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devcfg, /* devcfg interface (zynq) */
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max_xilinx_iface_type /* insert all new types before this */
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} Xilinx_iface; /* end, typedef Xilinx_iface */
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typedef enum { /* typedef Xilinx_Family */
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min_xilinx_type, /* low range check value */
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Xilinx_Spartan2, /* Spartan-II Family */
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Xilinx_VirtexE, /* Virtex-E Family */
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Xilinx_Virtex2, /* Virtex2 Family */
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Xilinx_Spartan3, /* Spartan-III Family */
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xilinx_zynq, /* Zynq Family */
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max_xilinx_type /* insert all new types before this */
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} Xilinx_Family; /* end, typedef Xilinx_Family */
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typedef struct { /* typedef Xilinx_desc */
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Xilinx_Family family; /* part type */
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Xilinx_iface iface; /* interface type */
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size_t size; /* bytes of data part can accept */
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void *iface_fns; /* interface function table */
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int cookie; /* implementation specific cookie */
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} Xilinx_desc; /* end, typedef Xilinx_desc */
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/* Generic Xilinx Functions
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*********************************************************************/
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extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size);
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extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
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extern int xilinx_info(Xilinx_desc *desc);
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/* Board specific implementation specific function types
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*********************************************************************/
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typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie );
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typedef int (*Xilinx_init_fn)( int cookie );
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typedef int (*Xilinx_err_fn)( int cookie );
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typedef int (*Xilinx_done_fn)( int cookie );
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typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie );
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typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie );
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typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie );
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typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie );
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typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie );
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typedef int (*Xilinx_busy_fn)( int cookie );
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typedef int (*Xilinx_abort_fn)( int cookie );
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typedef int (*Xilinx_pre_fn)( int cookie );
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typedef int (*Xilinx_post_fn)( int cookie );
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typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );
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#endif /* _XILINX_H_ */
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