mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-06 12:53:21 +09:00
d5dae85f23
Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
125 lines
2.9 KiB
C
125 lines
2.9 KiB
C
/*
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* Copyright (c) 2013 Xilinx Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <asm/arch/hardware.h>
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#define SLCR_LOCK_MAGIC 0x767B
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#define SLCR_UNLOCK_MAGIC 0xDF0D
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#define SLCR_IDCODE_MASK 0x1F000
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#define SLCR_IDCODE_SHIFT 12
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static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
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void zynq_slcr_lock(void)
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{
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if (!slcr_lock)
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writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
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}
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void zynq_slcr_unlock(void)
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{
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if (slcr_lock)
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writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
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}
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/* Reset the entire system */
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void zynq_slcr_cpu_reset(void)
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{
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/*
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* Unlock the SLCR then reset the system.
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* Note that this seems to require raw i/o
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* functions or there's a lockup?
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*/
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zynq_slcr_unlock();
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/*
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* Clear 0x0F000000 bits of reboot status register to workaround
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* the FSBL not loading the bitstream after soft-reboot
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* This is a temporary solution until we know more.
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*/
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clrbits_le32(&slcr_base->reboot_status, 0xF000000);
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writel(1, &slcr_base->pss_rst_ctrl);
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}
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/* Setup clk for network */
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void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
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{
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zynq_slcr_unlock();
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if (gem_id > 1) {
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printf("Non existing GEM id %d\n", gem_id);
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goto out;
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}
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if (gem_id) {
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/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
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writel(clk, &slcr_base->gem1_clk_ctrl);
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/* Configure GEM_RCLK_CTRL */
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writel(rclk, &slcr_base->gem1_rclk_ctrl);
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} else {
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/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
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writel(clk, &slcr_base->gem0_clk_ctrl);
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/* Configure GEM_RCLK_CTRL */
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writel(rclk, &slcr_base->gem0_rclk_ctrl);
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}
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out:
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zynq_slcr_lock();
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}
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void zynq_slcr_devcfg_disable(void)
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{
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zynq_slcr_unlock();
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/* Disable AXI interface */
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writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
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/* Set Level Shifters DT618760 */
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writel(0xA, &slcr_base->lvl_shftr_en);
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zynq_slcr_lock();
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}
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void zynq_slcr_devcfg_enable(void)
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{
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zynq_slcr_unlock();
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/* Set Level Shifters DT618760 */
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writel(0xF, &slcr_base->lvl_shftr_en);
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/* Disable AXI interface */
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writel(0x0, &slcr_base->fpga_rst_ctrl);
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zynq_slcr_lock();
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}
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u32 zynq_slcr_get_idcode(void)
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{
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return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
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SLCR_IDCODE_SHIFT;
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}
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