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https://github.com/brain-hackers/u-boot-brain
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83083febf5
In cases when the same SPL should run on boards with i.MX8MM, that differ in DDR configuration, it is necessary to try different parameters and check if the training done by the firmware suceeds or not. Therefore we return the DDR training/initialization success to the upper layer in order to be able to retry with different settings if necessary. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <linux/kernel.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/lpddr4_define.h>
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int ddr_cfg_phy(struct dram_timing_info *dram_timing)
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{
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struct dram_cfg_param *dram_cfg;
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struct dram_fsp_msg *fsp_msg;
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unsigned int num;
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int i = 0;
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int j = 0;
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int ret;
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/* initialize PHY configuration */
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dram_cfg = dram_timing->ddrphy_cfg;
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num = dram_timing->ddrphy_cfg_num;
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for (i = 0; i < num; i++) {
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/* config phy reg */
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dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
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dram_cfg++;
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}
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/* load the frequency setpoint message block config */
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fsp_msg = dram_timing->fsp_msg;
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for (i = 0; i < dram_timing->fsp_msg_num; i++) {
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debug("DRAM PHY training for %dMTS\n", fsp_msg->drate);
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/* set dram PHY input clocks to desired frequency */
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ddrphy_init_set_dfi_clk(fsp_msg->drate);
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/* load the dram training firmware image */
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dwc_ddrphy_apb_wr(0xd0000, 0x0);
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ddr_load_train_firmware(fsp_msg->fw_type);
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/* load the frequency set point message block parameter */
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dram_cfg = fsp_msg->fsp_cfg;
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num = fsp_msg->fsp_cfg_num;
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for (j = 0; j < num; j++) {
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dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
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dram_cfg++;
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}
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/*
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* -------------------- excute the firmware --------------------
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* Running the firmware is a simply process to taking the
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* PMU out of reset and stall, then the firwmare will be run
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* 1. reset the PMU;
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* 2. begin the excution;
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* 3. wait for the training done;
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* 4. read the message block result.
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* -------------------------------------------------------------
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*/
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dwc_ddrphy_apb_wr(0xd0000, 0x1);
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dwc_ddrphy_apb_wr(0xd0099, 0x9);
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dwc_ddrphy_apb_wr(0xd0099, 0x1);
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dwc_ddrphy_apb_wr(0xd0099, 0x0);
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/* Wait for the training firmware to complete */
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ret = wait_ddrphy_training_complete();
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if (ret)
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return ret;
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/* Halt the microcontroller. */
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dwc_ddrphy_apb_wr(0xd0099, 0x1);
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/* Read the Message Block results */
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dwc_ddrphy_apb_wr(0xd0000, 0x0);
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ddrphy_init_read_msg_block(fsp_msg->fw_type);
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dwc_ddrphy_apb_wr(0xd0000, 0x1);
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fsp_msg++;
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}
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/* Load PHY Init Engine Image */
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dram_cfg = dram_timing->ddrphy_pie;
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num = dram_timing->ddrphy_pie_num;
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for (i = 0; i < num; i++) {
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dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
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dram_cfg++;
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}
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/* save the ddr PHY trained CSR in memory for low power use */
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ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
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return 0;
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}
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