mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-11 12:43:45 +09:00
825ab6b406
Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
33 lines
724 B
Plaintext
33 lines
724 B
Plaintext
menu "i.MX8M DDR controllers"
|
|
depends on ARCH_IMX8M
|
|
|
|
config IMX8M_DRAM
|
|
bool "imx8m dram"
|
|
|
|
config IMX8M_LPDDR4
|
|
bool "imx8m lpddr4"
|
|
select IMX8M_DRAM
|
|
help
|
|
Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
|
|
|
|
config IMX8M_DDR4
|
|
bool "imx8m ddr4"
|
|
select IMX8M_DRAM
|
|
help
|
|
Select the i.MX8M DDR4 driver support on i.MX8M SOC.
|
|
|
|
config IMX8M_DDR3L
|
|
bool "imx8m ddr3l"
|
|
select IMX8M_DRAM
|
|
help
|
|
Select the i.MX8M DDR3L driver support on i.MX8M SOC.
|
|
|
|
config SAVED_DRAM_TIMING_BASE
|
|
hex "Define the base address for saved dram timing"
|
|
help
|
|
after DRAM is trained, need to save the dram related timming
|
|
info into memory for low power use. OCRAM_S is used for this
|
|
purpose on i.MX8MM.
|
|
default 0x180000
|
|
endmenu
|