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https://github.com/brain-hackers/u-boot-brain
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e9d6a20034
Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
69 lines
1.6 KiB
C
69 lines
1.6 KiB
C
/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/reset_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_reset_manager *reset_manager_base =
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(void *)SOCFPGA_RSTMGR_ADDRESS;
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/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
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void socfpga_watchdog_reset(void)
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{
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/* assert reset for watchdog */
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setbits_le32(&reset_manager_base->per_mod_reset,
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1 << RSTMGR_PERMODRST_L4WD0_LSB);
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/* deassert watchdog from reset (watchdog in not running state) */
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clrbits_le32(&reset_manager_base->per_mod_reset,
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1 << RSTMGR_PERMODRST_L4WD0_LSB);
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}
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/*
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* Write the reset manager register to cause reset
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*/
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void reset_cpu(ulong addr)
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{
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/* request a warm reset */
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writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
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&reset_manager_base->ctrl);
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/*
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* infinite loop here as watchdog will trigger and reset
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* the processor
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*/
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while (1)
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;
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}
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/*
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* Release peripherals from reset based on handoff
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*/
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void reset_deassert_peripherals_handoff(void)
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{
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writel(0, &reset_manager_base->per_mod_reset);
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}
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/* Change the reset state for EMAC 0 and EMAC 1 */
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void socfpga_emac_reset(int enable)
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{
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const void *reset = &reset_manager_base->per_mod_reset;
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if (enable) {
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setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
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setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
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} else {
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#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
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clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
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#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
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clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
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#endif
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}
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}
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