mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 21:33:24 +09:00
![Marek Vasut](/assets/img/avatar_default.png)
Rework the ULCB CPLD driver and make it into a sysreset driver, since that is what the ULCB CPLD driver is mostly for. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
192 lines
4.6 KiB
C
192 lines
4.6 KiB
C
/*
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* ULCB board CPLD access support
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*
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* Copyright (C) 2017 Renesas Electronics Corporation
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* Copyright (C) 2017 Cogent Embedded, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <errno.h>
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#include <linux/err.h>
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#include <sysreset.h>
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#define CPLD_ADDR_MODE 0x00 /* RW */
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#define CPLD_ADDR_MUX 0x02 /* RW */
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#define CPLD_ADDR_DIPSW6 0x08 /* R */
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#define CPLD_ADDR_RESET 0x80 /* RW */
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#define CPLD_ADDR_VERSION 0xFF /* R */
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struct renesas_ulcb_sysreset_priv {
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struct gpio_desc miso;
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struct gpio_desc mosi;
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struct gpio_desc sck;
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struct gpio_desc sstbz;
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};
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static u32 cpld_read(struct udevice *dev, u8 addr)
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{
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struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
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u32 data = 0;
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int i;
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for (i = 0; i < 8; i++) {
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dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */
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dm_gpio_set_value(&priv->sck, 1);
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addr <<= 1;
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dm_gpio_set_value(&priv->sck, 0);
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}
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dm_gpio_set_value(&priv->mosi, 0); /* READ */
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dm_gpio_set_value(&priv->sstbz, 0);
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dm_gpio_set_value(&priv->sck, 1);
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dm_gpio_set_value(&priv->sck, 0);
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dm_gpio_set_value(&priv->sstbz, 1);
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for (i = 0; i < 32; i++) {
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dm_gpio_set_value(&priv->sck, 1);
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data <<= 1;
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data |= dm_gpio_get_value(&priv->miso); /* MSB first */
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dm_gpio_set_value(&priv->sck, 0);
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}
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return data;
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}
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static void cpld_write(struct udevice *dev, u8 addr, u32 data)
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{
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struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
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int i;
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for (i = 0; i < 32; i++) {
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dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */
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dm_gpio_set_value(&priv->sck, 1);
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data <<= 1;
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dm_gpio_set_value(&priv->sck, 0);
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}
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for (i = 0; i < 8; i++) {
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dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */
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dm_gpio_set_value(&priv->sck, 1);
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addr <<= 1;
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dm_gpio_set_value(&priv->sck, 0);
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}
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dm_gpio_set_value(&priv->mosi, 1); /* WRITE */
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dm_gpio_set_value(&priv->sstbz, 0);
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dm_gpio_set_value(&priv->sck, 1);
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dm_gpio_set_value(&priv->sck, 0);
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dm_gpio_set_value(&priv->sstbz, 1);
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}
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static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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struct udevice *dev;
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u32 addr, val;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
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DM_GET_DRIVER(sysreset_renesas_ulcb),
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&dev);
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if (ret)
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return ret;
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if (argc == 2 && strcmp(argv[1], "info") == 0) {
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printf("CPLD version:\t\t\t0x%08x\n",
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cpld_read(dev, CPLD_ADDR_VERSION));
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printf("H3 Mode setting (MD0..28):\t0x%08x\n",
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cpld_read(dev, CPLD_ADDR_MODE));
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printf("Multiplexer settings:\t\t0x%08x\n",
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cpld_read(dev, CPLD_ADDR_MUX));
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printf("DIPSW (SW6):\t\t\t0x%08x\n",
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cpld_read(dev, CPLD_ADDR_DIPSW6));
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return 0;
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}
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if (argc < 3)
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return CMD_RET_USAGE;
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addr = simple_strtoul(argv[2], NULL, 16);
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if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
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addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 ||
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addr == CPLD_ADDR_RESET)) {
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printf("Invalid CPLD register address\n");
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return CMD_RET_USAGE;
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}
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if (argc == 3 && strcmp(argv[1], "read") == 0) {
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printf("0x%x\n", cpld_read(dev, addr));
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} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
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val = simple_strtoul(argv[3], NULL, 16);
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cpld_write(dev, addr, val);
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}
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return 0;
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}
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U_BOOT_CMD(
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cpld, 4, 1, do_cpld,
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"CPLD access",
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"info\n"
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"cpld read addr\n"
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"cpld write addr val\n"
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);
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static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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cpld_write(dev, CPLD_ADDR_RESET, 1);
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return -EINPROGRESS;
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}
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static int renesas_ulcb_sysreset_probe(struct udevice *dev)
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{
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struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
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if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
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GPIOD_IS_IN))
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return -EINVAL;
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if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck,
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GPIOD_IS_OUT))
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return -EINVAL;
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if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
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return -EINVAL;
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if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
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GPIOD_IS_OUT))
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return -EINVAL;
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/* PULL-UP on MISO line */
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setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
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/* Dummy read */
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cpld_read(dev, CPLD_ADDR_VERSION);
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return 0;
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}
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static struct sysreset_ops renesas_ulcb_sysreset = {
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.request = renesas_ulcb_sysreset_request,
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};
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static const struct udevice_id renesas_ulcb_sysreset_ids[] = {
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{ .compatible = "renesas,ulcb-cpld" },
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{ }
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};
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U_BOOT_DRIVER(sysreset_renesas_ulcb) = {
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.name = "renesas_ulcb_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &renesas_ulcb_sysreset,
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.probe = renesas_ulcb_sysreset_probe,
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.of_match = renesas_ulcb_sysreset_ids,
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.priv_auto_alloc_size = sizeof(struct renesas_ulcb_sysreset_priv),
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};
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