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![Sagar Shrikant Kadam](/assets/img/avatar_default.png)
PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
813 lines
22 KiB
C
813 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Copyright (C) 2018 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* The FU540 PRCI implements clock and reset control for the SiFive
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* FU540-C000 chip. This driver assumes that it has sole control
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* over all PRCI resources.
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*
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* This driver is based on the PRCI driver written by Wesley Terpstra.
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*
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* Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
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* https://github.com/riscv/riscv-linux
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*
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* References:
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* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/reset.h>
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#include <clk-uclass.h>
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#include <clk.h>
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#include <div64.h>
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#include <dm.h>
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#include <errno.h>
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#include <reset-uclass.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/math64.h>
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#include <linux/clk/analogbits-wrpll-cln28hpc.h>
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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#include <dt-bindings/reset/sifive-fu540-prci.h>
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/*
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* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
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* hfclk and rtcclk
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*/
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#define EXPECTED_CLK_PARENT_COUNT 2
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/*
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* Register offsets and bitmasks
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*/
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/* COREPLLCFG0 */
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#define PRCI_COREPLLCFG0_OFFSET 0x4
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#define PRCI_COREPLLCFG0_DIVR_SHIFT 0
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#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
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#define PRCI_COREPLLCFG0_DIVF_SHIFT 6
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#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
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#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
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#define PRCI_COREPLLCFG0_RANGE_SHIFT 18
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#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
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#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
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#define PRCI_COREPLLCFG0_FSE_SHIFT 25
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#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
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#define PRCI_COREPLLCFG0_LOCK_SHIFT 31
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#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
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/* COREPLLCFG1 */
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#define PRCI_COREPLLCFG1_OFFSET 0x8
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#define PRCI_COREPLLCFG1_CKE_SHIFT 31
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#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
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/* DDRPLLCFG0 */
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#define PRCI_DDRPLLCFG0_OFFSET 0xc
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#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
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#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
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#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
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#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
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#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
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#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
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#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
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#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
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#define PRCI_DDRPLLCFG0_FSE_SHIFT 25
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#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
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#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
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#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
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/* DDRPLLCFG1 */
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#define PRCI_DDRPLLCFG1_OFFSET 0x10
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#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
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#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
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/* GEMGXLPLLCFG0 */
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#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
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#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
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#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \
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(0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
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#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \
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(0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
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#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \
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(0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \
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(0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
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#define PRCI_GEMGXLPLLCFG0_FSE_MASK \
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(0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
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#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
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/* GEMGXLPLLCFG1 */
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#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
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#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
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#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
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/* CORECLKSEL */
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#define PRCI_CORECLKSEL_OFFSET 0x24
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#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
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#define PRCI_CORECLKSEL_CORECLKSEL_MASK \
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(0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
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/* DEVICESRESETREG */
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#define PRCI_DEVICESRESETREG_OFFSET 0x28
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#define PRCI_DEVICERESETCNT 5
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#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
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(0x1 << PRCI_RST_DDR_CTRL_N)
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#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
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(0x1 << PRCI_RST_DDR_AXI_N)
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#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
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(0x1 << PRCI_RST_DDR_AHB_N)
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#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
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(0x1 << PRCI_RST_DDR_PHY_N)
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#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
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(0x1 << PRCI_RST_GEMGXL_N)
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/* CLKMUXSTATUSREG */
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#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
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#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
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#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
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(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
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/* PROCMONCFG */
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#define PRCI_PROCMONCFG_OFFSET 0xF0
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#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
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#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
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(0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
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/*
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* Private structures
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*/
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/**
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* struct __prci_data - per-device-instance data
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* @va: base virtual address of the PRCI IP block
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* @parent: parent clk instance
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*
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* PRCI per-device instance data
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*/
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struct __prci_data {
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void *va;
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struct clk parent_hfclk;
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struct clk parent_rtcclk;
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};
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/**
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* struct __prci_wrpll_data - WRPLL configuration and integration data
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* @c: WRPLL current configuration record
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* @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
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* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
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* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
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* @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
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* @release_reset: fn ptr to code to release clock reset
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*
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* @enable_bypass and @disable_bypass are used for WRPLL instances
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* that contain a separate external glitchless clock mux downstream
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* from the PLL. The WRPLL internal bypass mux is not glitchless.
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*/
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struct __prci_wrpll_data {
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struct wrpll_cfg c;
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void (*enable_bypass)(struct __prci_data *pd);
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void (*disable_bypass)(struct __prci_data *pd);
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u8 cfg0_offs;
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u8 cfg1_offs;
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void (*release_reset)(struct __prci_data *pd);
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};
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struct __prci_clock;
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/* struct __prci_clock_ops - clock operations */
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struct __prci_clock_ops {
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int (*set_rate)(struct __prci_clock *pc,
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unsigned long rate,
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unsigned long parent_rate);
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unsigned long (*round_rate)(struct __prci_clock *pc,
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unsigned long rate,
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unsigned long *parent_rate);
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unsigned long (*recalc_rate)(struct __prci_clock *pc,
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unsigned long parent_rate);
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int (*enable_clk)(struct __prci_clock *pc, bool enable);
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};
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/**
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* struct __prci_clock - describes a clock device managed by PRCI
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* @name: user-readable clock name string - should match the manual
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* @parent_name: parent name for this clock
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* @ops: struct __prci_clock_ops for control
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* @pwd: WRPLL-specific data, associated with this clock (if not NULL)
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* @pd: PRCI-specific data associated with this clock (if not NULL)
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*
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* PRCI clock data. Used by the PRCI driver to register PRCI-provided
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* clocks to the Linux clock infrastructure.
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*/
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struct __prci_clock {
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const char *name;
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const char *parent_name;
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const struct __prci_clock_ops *ops;
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struct __prci_wrpll_data *pwd;
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struct __prci_data *pd;
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};
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/*
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* Private functions
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*/
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/**
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* __prci_readl() - read from a PRCI register
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* @pd: PRCI context
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* @offs: register offset to read from (in bytes, from PRCI base address)
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*
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* Read the register located at offset @offs from the base virtual
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* address of the PRCI register target described by @pd, and return
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* the value to the caller.
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*
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* Context: Any context.
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*
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* Return: the contents of the register described by @pd and @offs.
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*/
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static u32 __prci_readl(struct __prci_data *pd, u32 offs)
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{
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return readl(pd->va + offs);
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}
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static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
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{
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writel(v, pd->va + offs);
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}
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/* WRPLL-related private functions */
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/**
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* __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
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* @c: ptr to a struct wrpll_cfg record to write config into
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* @r: value read from the PRCI PLL configuration register
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*
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* Given a value @r read from an FU540 PRCI PLL configuration register,
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* split it into fields and populate it into the WRPLL configuration record
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* pointed to by @c.
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*
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* The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
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* have the same register layout.
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*
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* Context: Any context.
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*/
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static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
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{
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u32 v;
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v = r & PRCI_COREPLLCFG0_DIVR_MASK;
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v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
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c->divr = v;
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v = r & PRCI_COREPLLCFG0_DIVF_MASK;
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v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
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c->divf = v;
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v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
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v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
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c->divq = v;
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v = r & PRCI_COREPLLCFG0_RANGE_MASK;
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v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
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c->range = v;
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c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
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WRPLL_FLAGS_EXT_FEEDBACK_MASK);
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/* external feedback mode not supported */
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c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
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}
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/**
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* __prci_wrpll_pack() - pack PLL configuration parameters into a register value
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* @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
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*
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* Using a set of WRPLL configuration values pointed to by @c,
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* assemble a PRCI PLL configuration register value, and return it to
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* the caller.
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*
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* Context: Any context. Caller must ensure that the contents of the
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* record pointed to by @c do not change during the execution
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* of this function.
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*
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* Returns: a value suitable for writing into a PRCI PLL configuration
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* register
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*/
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static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
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{
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u32 r = 0;
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r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
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r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
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r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
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r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
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/* external feedback mode not supported */
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r |= PRCI_COREPLLCFG0_FSE_MASK;
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return r;
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}
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/**
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* __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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*
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* Read the current configuration of the PLL identified by @pwd from
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* the PRCI identified by @pd, and store it into the local configuration
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* cache in @pwd.
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*
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* Context: Any context. Caller must prevent the records pointed to by
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* @pd and @pwd from changing during execution.
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*/
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static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd)
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{
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__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
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}
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/**
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* __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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* @c: WRPLL configuration record to write
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*
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* Write the WRPLL configuration described by @c into the WRPLL
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* configuration register identified by @pwd in the PRCI instance
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* described by @c. Make a cached copy of the WRPLL's current
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* configuration so it can be used by other code.
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*
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* Context: Any context. Caller must prevent the records pointed to by
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* @pd and @pwd from changing during execution.
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*/
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static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd,
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struct wrpll_cfg *c)
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{
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__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
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memcpy(&pwd->c, c, sizeof(*c));
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}
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/**
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* __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
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* into the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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* @enable: Clock enable or disable value
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*/
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static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd,
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u32 enable)
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{
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__prci_writel(enable, pwd->cfg1_offs, pd);
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}
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/* Core clock mux control */
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/**
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* __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
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* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
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*
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* Switch the CORECLK mux to the HFCLK input source; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_CORECLKSEL_OFFSET register.
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*/
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static void __prci_coreclksel_use_hfclk(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
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r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
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__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
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}
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/**
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* __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
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* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
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*
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* Switch the CORECLK mux to the PLL output clock; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_CORECLKSEL_OFFSET register.
|
|
*/
|
|
static void __prci_coreclksel_use_corepll(struct __prci_data *pd)
|
|
{
|
|
u32 r;
|
|
|
|
r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
|
|
r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
|
|
__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
|
|
|
|
r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
|
|
}
|
|
|
|
static unsigned long sifive_fu540_prci_wrpll_recalc_rate(
|
|
struct __prci_clock *pc,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct __prci_wrpll_data *pwd = pc->pwd;
|
|
|
|
return wrpll_calc_output_rate(&pwd->c, parent_rate);
|
|
}
|
|
|
|
static unsigned long sifive_fu540_prci_wrpll_round_rate(
|
|
struct __prci_clock *pc,
|
|
unsigned long rate,
|
|
unsigned long *parent_rate)
|
|
{
|
|
struct __prci_wrpll_data *pwd = pc->pwd;
|
|
struct wrpll_cfg c;
|
|
|
|
memcpy(&c, &pwd->c, sizeof(c));
|
|
|
|
wrpll_configure_for_rate(&c, rate, *parent_rate);
|
|
|
|
return wrpll_calc_output_rate(&c, *parent_rate);
|
|
}
|
|
|
|
static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
|
|
unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct __prci_wrpll_data *pwd = pc->pwd;
|
|
struct __prci_data *pd = pc->pd;
|
|
int r;
|
|
|
|
r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
|
|
if (r)
|
|
return r;
|
|
|
|
if (pwd->enable_bypass)
|
|
pwd->enable_bypass(pd);
|
|
|
|
__prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
|
|
|
|
udelay(wrpll_calc_max_lock_us(&pwd->c));
|
|
|
|
if (pwd->disable_bypass)
|
|
pwd->disable_bypass(pd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable)
|
|
{
|
|
struct __prci_wrpll_data *pwd = pc->pwd;
|
|
struct __prci_data *pd = pc->pd;
|
|
|
|
if (enable) {
|
|
__prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
|
|
|
|
if (pwd->release_reset)
|
|
pwd->release_reset(pd);
|
|
} else {
|
|
u32 r;
|
|
|
|
r = __prci_readl(pd, pwd->cfg1_offs);
|
|
r &= ~PRCI_COREPLLCFG1_CKE_MASK;
|
|
|
|
__prci_wrpll_write_cfg1(pd, pwd, r);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
|
|
.set_rate = sifive_fu540_prci_wrpll_set_rate,
|
|
.round_rate = sifive_fu540_prci_wrpll_round_rate,
|
|
.recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
|
|
.enable_clk = sifive_fu540_prci_clock_enable,
|
|
};
|
|
|
|
/* TLCLKSEL clock integration */
|
|
|
|
static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(
|
|
struct __prci_clock *pc,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct __prci_data *pd = pc->pd;
|
|
u32 v;
|
|
u8 div;
|
|
|
|
v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
|
|
v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
|
|
div = v ? 1 : 2;
|
|
|
|
return div_u64(parent_rate, div);
|
|
}
|
|
|
|
static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
|
|
.recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
|
|
};
|
|
|
|
static int __prci_consumer_reset(const char *rst_name, bool trigger)
|
|
{
|
|
struct udevice *dev;
|
|
struct reset_ctl rst_sig;
|
|
int ret;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_RESET,
|
|
DM_GET_DRIVER(sifive_reset),
|
|
&dev);
|
|
if (ret) {
|
|
dev_err(dev, "Reset driver not found: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = reset_get_by_name(dev, rst_name, &rst_sig);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get %s reset\n", rst_name);
|
|
return ret;
|
|
}
|
|
|
|
if (reset_valid(&rst_sig)) {
|
|
if (trigger)
|
|
ret = reset_deassert(&rst_sig);
|
|
else
|
|
ret = reset_assert(&rst_sig);
|
|
if (ret) {
|
|
dev_err(dev, "failed to trigger reset id = %ld\n",
|
|
rst_sig.id);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* __prci_ddr_release_reset() - Release DDR reset
|
|
* @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
|
|
*
|
|
*/
|
|
static void __prci_ddr_release_reset(struct __prci_data *pd)
|
|
{
|
|
/* Release DDR ctrl reset */
|
|
__prci_consumer_reset("ddr_ctrl", true);
|
|
|
|
/* HACK to get the '1 full controller clock cycle'. */
|
|
asm volatile ("fence");
|
|
|
|
/* Release DDR AXI reset */
|
|
__prci_consumer_reset("ddr_axi", true);
|
|
|
|
/* Release DDR AHB reset */
|
|
__prci_consumer_reset("ddr_ahb", true);
|
|
|
|
/* Release DDR PHY reset */
|
|
__prci_consumer_reset("ddr_phy", true);
|
|
|
|
/* HACK to get the '1 full controller clock cycle'. */
|
|
asm volatile ("fence");
|
|
|
|
/*
|
|
* These take like 16 cycles to actually propagate. We can't go sending
|
|
* stuff before they come out of reset. So wait.
|
|
*/
|
|
for (int i = 0; i < 256; i++)
|
|
asm volatile ("nop");
|
|
}
|
|
|
|
/**
|
|
* __prci_ethernet_release_reset() - Release ethernet reset
|
|
* @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
|
|
*
|
|
*/
|
|
static void __prci_ethernet_release_reset(struct __prci_data *pd)
|
|
{
|
|
/* Release GEMGXL reset */
|
|
__prci_consumer_reset("gemgxl_reset", true);
|
|
|
|
/* Procmon => core clock */
|
|
__prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
|
|
pd);
|
|
}
|
|
|
|
/*
|
|
* PRCI integration data for each WRPLL instance
|
|
*/
|
|
|
|
static struct __prci_wrpll_data __prci_corepll_data = {
|
|
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
|
|
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
|
|
.enable_bypass = __prci_coreclksel_use_hfclk,
|
|
.disable_bypass = __prci_coreclksel_use_corepll,
|
|
};
|
|
|
|
static struct __prci_wrpll_data __prci_ddrpll_data = {
|
|
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
|
|
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
|
|
.release_reset = __prci_ddr_release_reset,
|
|
};
|
|
|
|
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
|
|
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
|
|
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
|
|
.release_reset = __prci_ethernet_release_reset,
|
|
};
|
|
|
|
/*
|
|
* List of clock controls provided by the PRCI
|
|
*/
|
|
|
|
static struct __prci_clock __prci_init_clocks[] = {
|
|
[PRCI_CLK_COREPLL] = {
|
|
.name = "corepll",
|
|
.parent_name = "hfclk",
|
|
.ops = &sifive_fu540_prci_wrpll_clk_ops,
|
|
.pwd = &__prci_corepll_data,
|
|
},
|
|
[PRCI_CLK_DDRPLL] = {
|
|
.name = "ddrpll",
|
|
.parent_name = "hfclk",
|
|
.ops = &sifive_fu540_prci_wrpll_clk_ops,
|
|
.pwd = &__prci_ddrpll_data,
|
|
},
|
|
[PRCI_CLK_GEMGXLPLL] = {
|
|
.name = "gemgxlpll",
|
|
.parent_name = "hfclk",
|
|
.ops = &sifive_fu540_prci_wrpll_clk_ops,
|
|
.pwd = &__prci_gemgxlpll_data,
|
|
},
|
|
[PRCI_CLK_TLCLK] = {
|
|
.name = "tlclk",
|
|
.parent_name = "corepll",
|
|
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
|
|
},
|
|
};
|
|
|
|
static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc)
|
|
{
|
|
ulong parent_rate;
|
|
struct __prci_clock *p;
|
|
|
|
if (strcmp(pc->parent_name, "corepll") == 0) {
|
|
p = &__prci_init_clocks[PRCI_CLK_COREPLL];
|
|
if (!p->pd || !p->ops->recalc_rate)
|
|
return -ENXIO;
|
|
|
|
return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p));
|
|
}
|
|
|
|
if (strcmp(pc->parent_name, "rtcclk") == 0)
|
|
parent_rate = clk_get_rate(&pc->pd->parent_rtcclk);
|
|
else
|
|
parent_rate = clk_get_rate(&pc->pd->parent_hfclk);
|
|
|
|
return parent_rate;
|
|
}
|
|
|
|
static ulong sifive_fu540_prci_get_rate(struct clk *clk)
|
|
{
|
|
struct __prci_clock *pc;
|
|
|
|
if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
|
|
return -ENXIO;
|
|
|
|
pc = &__prci_init_clocks[clk->id];
|
|
if (!pc->pd || !pc->ops->recalc_rate)
|
|
return -ENXIO;
|
|
|
|
return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc));
|
|
}
|
|
|
|
static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
int err;
|
|
struct __prci_clock *pc;
|
|
|
|
if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
|
|
return -ENXIO;
|
|
|
|
pc = &__prci_init_clocks[clk->id];
|
|
if (!pc->pd || !pc->ops->set_rate)
|
|
return -ENXIO;
|
|
|
|
err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc));
|
|
if (err)
|
|
return err;
|
|
|
|
return rate;
|
|
}
|
|
|
|
static int sifive_fu540_prci_enable(struct clk *clk)
|
|
{
|
|
struct __prci_clock *pc;
|
|
int ret = 0;
|
|
|
|
if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
|
|
return -ENXIO;
|
|
|
|
pc = &__prci_init_clocks[clk->id];
|
|
if (!pc->pd)
|
|
return -ENXIO;
|
|
|
|
if (pc->ops->enable_clk)
|
|
ret = pc->ops->enable_clk(pc, 1);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sifive_fu540_prci_disable(struct clk *clk)
|
|
{
|
|
struct __prci_clock *pc;
|
|
int ret = 0;
|
|
|
|
if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
|
|
return -ENXIO;
|
|
|
|
pc = &__prci_init_clocks[clk->id];
|
|
if (!pc->pd)
|
|
return -ENXIO;
|
|
|
|
if (pc->ops->enable_clk)
|
|
ret = pc->ops->enable_clk(pc, 0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sifive_fu540_prci_probe(struct udevice *dev)
|
|
{
|
|
int i, err;
|
|
struct __prci_clock *pc;
|
|
struct __prci_data *pd = dev_get_priv(dev);
|
|
|
|
pd->va = (void *)dev_read_addr(dev);
|
|
if (IS_ERR(pd->va))
|
|
return PTR_ERR(pd->va);
|
|
|
|
err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_get_by_index(dev, 1, &pd->parent_rtcclk);
|
|
if (err)
|
|
return err;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) {
|
|
pc = &__prci_init_clocks[i];
|
|
pc->pd = pd;
|
|
if (pc->pwd)
|
|
__prci_wrpll_read_cfg0(pd, pc->pwd);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops sifive_fu540_prci_ops = {
|
|
.set_rate = sifive_fu540_prci_set_rate,
|
|
.get_rate = sifive_fu540_prci_get_rate,
|
|
.enable = sifive_fu540_prci_enable,
|
|
.disable = sifive_fu540_prci_disable,
|
|
};
|
|
|
|
static int sifive_fu540_clk_bind(struct udevice *dev)
|
|
{
|
|
return sifive_reset_bind(dev, PRCI_DEVICERESETCNT);
|
|
}
|
|
|
|
static const struct udevice_id sifive_fu540_prci_ids[] = {
|
|
{ .compatible = "sifive,fu540-c000-prci" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(sifive_fu540_prci) = {
|
|
.name = "sifive-fu540-prci",
|
|
.id = UCLASS_CLK,
|
|
.of_match = sifive_fu540_prci_ids,
|
|
.probe = sifive_fu540_prci_probe,
|
|
.ops = &sifive_fu540_prci_ops,
|
|
.priv_auto_alloc_size = sizeof(struct __prci_data),
|
|
.bind = sifive_fu540_clk_bind,
|
|
};
|