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https://github.com/brain-hackers/u-boot-brain
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d473f0c621
The MMU range table can vary depending on things we may only find out at runtime. While the very simple ThunderX variant does not change, other boards will, so move the definition from a static entry in a header file to the board file. Signed-off-by: Alexander Graf <agraf@suse.de>
127 lines
2.1 KiB
C
127 lines
2.1 KiB
C
/**
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* (C) Copyright 2014, Cavium Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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**/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <linux/compiler.h>
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#include <cavium/atf.h>
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#include <asm/armv8/mmu.h>
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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#include <dm/platdata.h>
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#include <dm/platform_data/serial_pl01x.h>
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static const struct pl01x_serial_platdata serial0 = {
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.base = CONFIG_SYS_SERIAL0,
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.type = TYPE_PL011,
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.clock = 0,
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.skip_init = true,
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};
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U_BOOT_DEVICE(thunderx_serial0) = {
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.name = "serial_pl01x",
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.platdata = &serial0,
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};
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static const struct pl01x_serial_platdata serial1 = {
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.base = CONFIG_SYS_SERIAL1,
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.type = TYPE_PL011,
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.clock = 0,
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.skip_init = true,
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};
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U_BOOT_DEVICE(thunderx_serial1) = {
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.name = "serial_pl01x",
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.platdata = &serial1,
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};
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region thunderx_mem_map[] = {
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{
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.base = 0x000000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
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}, {
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.base = 0x800000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE,
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}, {
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.base = 0x840000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE,
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = thunderx_mem_map;
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int board_init(void)
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{
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return 0;
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}
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int timer_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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ssize_t node_count = atf_node_count();
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ssize_t dram_size;
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int node;
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printf("Initializing\nNodes in system: %zd\n", node_count);
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gd->ram_size = 0;
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for (node = 0; node < node_count; node++) {
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dram_size = atf_dram_size(node);
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printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
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gd->ram_size += dram_size;
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}
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gd->ram_size -= MEM_BASE;
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*(unsigned long *)CPU_RELEASE_ADDR = 0;
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puts("DRAM size:");
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return 0;
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}
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/*
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* Board specific reset that is system reset.
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*/
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void reset_cpu(ulong addr)
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{
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}
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/*
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* Board specific ethernet initialization routine.
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*/
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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return rc;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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printf("DEBUG: PCI Init TODO *****\n");
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}
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#endif
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