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https://github.com/brain-hackers/u-boot-brain
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d4b9106609
Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c. The unified driver can initialize data using DDR controller. No need to use DMA if just to initialze for ECC. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
108 lines
3.1 KiB
C
108 lines
3.1 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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struct board_specific_parameters {
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u32 datarate_mhz_low;
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u32 datarate_mhz_high;
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u32 n_ranks;
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u32 clk_adjust;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2T;
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};
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const struct board_specific_parameters board_specific_parameters_udimm[][20] = {
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{
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/*
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* memory controller 0
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* lo| hi| num| clk| cpo|wrdata|2T
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* mhz| mhz|ranks|adjst| | delay|
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*/
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{ 0, 300, 2, 4, 4, 2, 0},
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{301, 365, 2, 4, 6, 2, 0},
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{366, 450, 2, 4, 7, 2, 0},
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{451, 850, 2, 4, 31, 2, 0},
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{ 0, 300, 1, 4, 4, 2, 0},
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{301, 365, 1, 4, 6, 2, 0},
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{366, 450, 1, 4, 7, 2, 0},
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{451, 850, 1, 4, 31, 2, 0}
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}
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp;
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u32 num_params;
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u32 i, dimm_num;
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ulong ddr_freq;
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if (ctrl_num != 0) /* we have only one controller */
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return;
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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if (pdimm[i].n_ranks)
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break;
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}
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if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
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return;
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dimm_num = i;
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pbsp = &(board_specific_parameters_udimm[ctrl_num][0]);
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num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) /
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sizeof(board_specific_parameters_udimm[0][0]);
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < num_params; i++) {
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if (ddr_freq >= pbsp->datarate_mhz_low &&
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ddr_freq <= pbsp->datarate_mhz_high &&
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pdimm[dimm_num].n_ranks == pbsp->n_ranks) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay = pbsp->write_data_delay;
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popts->twoT_en = pbsp->force_2T;
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break;
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}
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pbsp++;
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}
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if (i == num_params) {
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printf("Warning: board specific timing not found "
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"for data rate %lu MT/s!\n", ddr_freq);
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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popts->DQS_config = 0; /* only true DQS signal is used on board */
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}
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