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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
This header file is now only used by files that access internal environment features. Drop it from various places where it is not needed. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
332 lines
7.9 KiB
C
332 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot board functions for CompuLab CL-SOM-iMX7 module
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*
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* (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
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*
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* Author: Uri Mashiach <uri.mashiach@compulab.co.il>
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*/
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#include <common.h>
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#include <env.h>
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#include <mmc.h>
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#include <phy.h>
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#include <netdev.h>
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#include <fsl_esdhc_imx.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/arch-mx7/mx7-pins.h>
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#include <asm/arch-mx7/sys_proto.h>
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#include <asm/arch-mx7/clock.h>
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#include "../common/eeprom.h"
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#include "common.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SYS_I2C_MXC
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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS)
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#define CL_SOM_IMX7_GPIO_I2C2_SCL IMX_GPIO_NR(1, 6)
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#define CL_SOM_IMX7_GPIO_I2C2_SDA IMX_GPIO_NR(1, 7)
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static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL |
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MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 |
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MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = CL_SOM_IMX7_GPIO_I2C2_SCL,
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},
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.sda = {
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.i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA |
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MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 |
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MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = CL_SOM_IMX7_GPIO_I2C2_SDA,
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},
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};
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/*
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* cl_som_imx7_setup_i2c() - I2C pinmux configuration.
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*/
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static void cl_som_imx7_setup_i2c(void)
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{
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2);
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}
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#else /* !CONFIG_SYS_I2C_MXC */
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static void cl_som_imx7_setup_i2c(void) {}
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#endif /* CONFIG_SYS_I2C_MXC */
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC_IMX
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#define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11)
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static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = {
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{USDHC1_BASE_ADDR, 0, 4},
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{USDHC3_BASE_ADDR},
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};
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-boot device node) (Physical Port)
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* mmc0 USDHC1
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* mmc2 USDHC3 (eMMC)
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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cl_som_imx7_usdhc1_pads_set();
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gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd");
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cl_som_imx7_usdhc_cfg[0].sdhc_clk =
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mxc_get_clock(MXC_ESDHC_CLK);
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break;
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case 1:
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cl_som_imx7_usdhc3_emmc_pads_set();
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gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr");
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gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0);
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udelay(500);
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gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1);
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cl_som_imx7_usdhc_cfg[1].sdhc_clk =
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mxc_get_clock(MXC_ESDHC3_CLK);
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break;
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default:
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printf("Warning: you configured more USDHC controllers "
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"(%d) than supported by the board\n", i + 1);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif /* CONFIG_FSL_ESDHC_IMX */
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#ifdef CONFIG_FEC_MXC
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#define CL_SOM_IMX7_ETH1_PHY_NRST IMX_GPIO_NR(1, 4)
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/*
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* cl_som_imx7_rgmii_rework() - Ethernet PHY configuration.
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*/
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static void cl_som_imx7_rgmii_rework(struct phy_device *phydev)
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{
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unsigned short val;
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/* Ar8031 phy SmartEEE feature cause link status generates glitch,
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* which cause ethernet link down/up issue, so disable SmartEEE
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*/
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= ~(0x1 << 8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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cl_som_imx7_rgmii_rework(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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/*
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* cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment.
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*
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* @env_var: MAC address environment variable
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* @eeprom_bus: I2C bus of the environment EEPROM
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*
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* @return: 0 on success, < 0 on failure
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*/
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static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus)
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{
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int ret;
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unsigned char enetaddr[6];
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ret = eth_env_get_enetaddr(env_var, enetaddr);
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if (ret)
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return 0;
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ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
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if (ret)
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return ret;
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ret = is_valid_ethaddr(enetaddr);
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if (!ret)
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return -1;
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return eth_env_set_enetaddr(env_var, enetaddr);
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}
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#define CL_SOM_IMX7_FEC_DEV_ID_PRI 0
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int board_eth_init(bd_t *bis)
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{
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/* set Ethernet MAC address environment */
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cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS);
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/* Ethernet interface pinmux configuration */
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cl_som_imx7_phy1_rst_pads_set();
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cl_som_imx7_fec1_pads_set();
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/* PHY reset */
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gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst");
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gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0);
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mdelay(10);
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gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
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/* MAC initialization */
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return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
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CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
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}
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/*
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* cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration.
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* - ENET1 reference clock mode select.
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* - ENET1_TX_CLK output driver is disabled when configured for ALT1.
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*/
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static void cl_som_imx7_setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
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= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
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clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
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(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
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IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
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set_clk_enet(ENET_125MHZ);
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}
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#else /* !CONFIG_FEC_MXC */
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static void cl_som_imx7_setup_fec(void) {}
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#endif /* CONFIG_FEC_MXC */
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#ifdef CONFIG_SPI
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static void cl_som_imx7_spi_init(void)
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{
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cl_som_imx7_espi1_pads_set();
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}
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#else /* !CONFIG_SPI */
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static void cl_som_imx7_spi_init(void) {}
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#endif /* CONFIG_SPI */
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int board_early_init_f(void)
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{
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cl_som_imx7_uart1_pads_set();
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cl_som_imx7_usb_otg1_pads_set();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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cl_som_imx7_setup_i2c();
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cl_som_imx7_setup_fec();
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cl_som_imx7_spi_init();
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return 0;
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}
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#ifdef CONFIG_POWER
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#define I2C_PMIC 0
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int power_init_board(void)
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{
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struct pmic *p;
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int ret;
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unsigned int reg, rev_id;
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ret = power_pfuze3000_init(I2C_PMIC);
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if (ret)
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return ret;
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p = pmic_get("PFUZE3000");
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ret = pmic_probe(p);
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if (ret)
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return ret;
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pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
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pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
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printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
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/* disable Low Power Mode during standby mode */
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pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
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return 0;
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}
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#endif /* CONFIG_POWER */
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/*
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* cl_som_imx7_setup_wdog() - watchdog configuration.
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* - Output WDOG_B signal to reset external pmic.
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* - Suspend the watchdog timer during low-power modes.
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*/
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void cl_som_imx7_setup_wdog(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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cl_som_imx7_wdog_pads_set();
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set_wdog_reset(wdog);
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/*
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* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
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* since we use PMIC_PWRON to reset the board.
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*/
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clrsetbits_le16(&wdog->wcr, 0, 0x10);
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}
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int board_late_init(void)
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{
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env_set("board_name", "CL-SOM-iMX7");
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cl_som_imx7_setup_wdog();
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return 0;
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}
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int checkboard(void)
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{
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char *mode;
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if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
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mode = "secure";
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else
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mode = "non-secure";
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printf("Board: CL-SOM-iMX7 in %s mode\n", mode);
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return 0;
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}
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