mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
d496162c85
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very top of 32-bit address space, so that it can be executed in place and read simply by copying from memory. For an 8MB ROM the mapping starts at 0xff800000. However some recent Intel CPUs do not use a simple 1:1 memory map. Instead the map starts at a different address and not all of the SPI flash is accessible through the map. This 'Fast SPI' feature requires that U-Boot check the location of the map. It is also possible (optionally) to read from the SPI flash using a driver. Add support for booting from Fast SPI. The memory-mapped version is used by both TPL and SPL on Apollo Lake. In respect of a SPI flash driver, the actual SPI driver is ich.c - this just adds a few helper functions and definitions. This is used by Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
27 lines
602 B
Makefile
27 lines
602 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2016 Google, Inc
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ifdef CONFIG_HAVE_MRC
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obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
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endif
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obj-y += cpu.o
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obj-y += fast_spi.o
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obj-y += lpc.o
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ifndef CONFIG_TARGET_EFI_APP
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
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ifndef CONFIG_$(SPL_)X86_64
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obj-y += microcode.o
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endif
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endif
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obj-y += pch.o
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ifdef CONFIG_SPL
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ifndef CONFIG_SPL_BUILD
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obj-y += cpu_from_spl.o
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endif
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endif
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