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https://github.com/brain-hackers/u-boot-brain
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![Icenowy Zheng](/assets/img/avatar_default.png)
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When it mismatches the real voltage supplied to the VCC to the PIO supply, the PIO will work improperly. The PIO controller also has a register that contains the status of each VCC rail of the PIO supplies, and it has the same definition with the configuration register. so we can just copy the content of this register to the configuration register at startup, to ensure the configuration is correct at startup stage. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> [jagan: s/__maybe__unused/__maybe_unused] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
324 lines
10 KiB
C
324 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some init for sunxi platform.
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*/
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#include <common.h>
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#include <mmc.h>
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#include <i2c.h>
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#include <serial.h>
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#include <spl.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/tzpc.h>
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#include <asm/arch/mmc.h>
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#include <linux/compiler.h>
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struct fel_stash {
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uint32_t sp;
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uint32_t lr;
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uint32_t cpsr;
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uint32_t sctlr;
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uint32_t vbar;
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uint32_t cr;
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};
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struct fel_stash fel_stash __attribute__((section(".data")));
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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static struct mm_region sunxi_mem_map[] = {
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{
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/* SRAM, MMIO regions */
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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}, {
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/* RAM */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0xC0000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = sunxi_mem_map;
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#endif
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static int gpio_init(void)
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{
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__maybe_unused uint val;
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#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
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#if defined(CONFIG_MACH_SUN4I) || \
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defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40)
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/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
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sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
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#endif
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#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
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sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
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#else
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sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
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#endif
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sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
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#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
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defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40))
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sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
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sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
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sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
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sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
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sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
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sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
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sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
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sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
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sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
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sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
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#else
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#error Unsupported console port number. Please fix pin mux settings in board.c
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#endif
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#ifdef CONFIG_MACH_SUN50I_H6
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/* Update PIO power bias configuration by copy hardware detected value */
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val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
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writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
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val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
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writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
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#endif
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return 0;
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}
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#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
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static int spl_board_load_image(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
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return_to_fel(fel_stash.sp, fel_stash.lr);
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return 0;
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}
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SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
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#endif
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void s_init(void)
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{
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/*
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* Undocumented magic taken from boot0, without this DRAM
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* access gets messed up (seems cache related).
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* The boot0 sources describe this as: "config ema for cache sram"
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*/
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#if defined CONFIG_MACH_SUN6I
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setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
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#elif defined CONFIG_MACH_SUN8I
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__maybe_unused uint version;
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/* Unlock sram version info reg, read it, relock */
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setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
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version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
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clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
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/*
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* Ideally this would be a switch case, but we do not know exactly
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* which versions there are and which version needs which settings,
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* so reproduce the per SoC code from the BSP.
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*/
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#if defined CONFIG_MACH_SUN8I_A23
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if (version == 0x1650)
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setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
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else /* 0x1661 ? */
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setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
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#elif defined CONFIG_MACH_SUN8I_A33
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if (version != 0x1667)
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setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
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#endif
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/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
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/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
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#endif
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#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
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/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 1\n"
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"orr r0, r0, #1 << 6\n"
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"mcr p15, 0, r0, c1, c0, 1\n"
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::: "r0");
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#endif
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#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
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/* Enable non-secure access to some peripherals */
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tzpc_init();
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#endif
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clock_init();
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timer_init();
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gpio_init();
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#ifndef CONFIG_DM_I2C
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i2c_init_board();
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#endif
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eth_init_board();
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}
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/* The sunxi internal brom will try to loader external bootloader
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* from mmc0, nand flash, mmc2.
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*/
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uint32_t sunxi_get_boot_device(void)
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{
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int boot_source;
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/*
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* When booting from the SD card or NAND memory, the "eGON.BT0"
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* signature is expected to be found in memory at the address 0x0004
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* (see the "mksunxiboot" tool, which generates this header).
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*
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* When booting in the FEL mode over USB, this signature is patched in
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* memory and replaced with something else by the 'fel' tool. This other
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* signature is selected in such a way, that it can't be present in a
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* valid bootable SD card image (because the BROM would refuse to
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* execute the SPL in this case).
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*
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* This checks for the signature and if it is not found returns to
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* the FEL code in the BROM to wait and receive the main u-boot
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* binary over USB. If it is found, it determines where SPL was
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* read from.
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*/
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if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
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return BOOT_DEVICE_BOARD;
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boot_source = readb(SPL_ADDR + 0x28);
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switch (boot_source) {
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case SUNXI_BOOTED_FROM_MMC0:
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case SUNXI_BOOTED_FROM_MMC0_HIGH:
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return BOOT_DEVICE_MMC1;
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case SUNXI_BOOTED_FROM_NAND:
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return BOOT_DEVICE_NAND;
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case SUNXI_BOOTED_FROM_MMC2:
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case SUNXI_BOOTED_FROM_MMC2_HIGH:
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return BOOT_DEVICE_MMC2;
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case SUNXI_BOOTED_FROM_SPI:
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return BOOT_DEVICE_SPI;
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}
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panic("Unknown boot source %d\n", boot_source);
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return -1; /* Never reached */
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}
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#ifdef CONFIG_SPL_BUILD
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u32 spl_boot_device(void)
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{
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return sunxi_get_boot_device();
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}
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void board_init_f(ulong dummy)
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{
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spl_init();
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preloader_console_init();
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#ifdef CONFIG_SPL_I2C_SUPPORT
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/* Needed early by sunxi_board_init if PMU is enabled */
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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#endif
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sunxi_board_init();
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}
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#endif
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void reset_cpu(ulong addr)
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{
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#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
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static const struct sunxi_wdog *wdog =
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&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
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/* Set the watchdog for its shortest interval (.5s) and wait */
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writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
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writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
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while (1) {
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/* sun5i sometimes gets stuck without this */
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writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
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}
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#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
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#if defined(CONFIG_MACH_SUN50I_H6)
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/* WDOG is broken for some H6 rev. use the R_WDOG instead */
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static const struct sunxi_wdog *wdog =
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(struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
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#else
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static const struct sunxi_wdog *wdog =
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((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
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#endif
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/* Set the watchdog for its shortest interval (.5s) and wait */
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writel(WDT_CFG_RESET, &wdog->cfg);
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writel(WDT_MODE_EN, &wdog->mode);
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writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
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while (1) { }
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#endif
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}
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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