mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
293 lines
8.4 KiB
C
293 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <asm/armv7.h>
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#include <asm/processor.h>
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#include "cache-uniphier.h"
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/* control registers */
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#define UNIPHIER_SSCC 0x500c0000 /* Control Register */
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#define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */
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#define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */
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#define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */
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#define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */
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#define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
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#define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */
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#define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */
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/* revision registers */
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#define UNIPHIER_SSCID 0x503c0100 /* ID Register */
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/* operation registers */
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#define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
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#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */
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#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */
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#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */
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#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
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#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
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#define UNIPHIER_SSCOQM 0x506c0248
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#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21)
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#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21)
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#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21)
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#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21)
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#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
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#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
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#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
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#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17)
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#define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */
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#define UNIPHIER_SSCOQM_CW (0x1 << 14)
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#define UNIPHIER_SSCOQM_CM_MASK (0x7)
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#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
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#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
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#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
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#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
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#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */
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#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */
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#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */
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#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */
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#define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */
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#define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */
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#define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */
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#define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */
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#define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */
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#define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1)
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#define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0)
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#define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */
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#define UNIPHIER_SSCOLPQS_EF (0x1 << 2)
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#define UNIPHIER_SSCOLPQS_EST (0x1 << 1)
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#define UNIPHIER_SSCOLPQS_QST (0x1 << 0)
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#define UNIPHIER_SSC_LINE_SIZE 128
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#define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE))
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#define UNIPHIER_SSCOQAD_IS_NEEDED(op) \
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((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
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#define UNIPHIER_SSCOQWM_IS_NEEDED(op) \
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(((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_WAY) || \
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((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY))
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/* uniphier_cache_sync - perform a sync point for a particular cache level */
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static void uniphier_cache_sync(void)
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{
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/* drain internal buffers */
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writel(UNIPHIER_SSCOPE_CM_SYNC, UNIPHIER_SSCOPE);
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/* need a read back to confirm */
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readl(UNIPHIER_SSCOPE);
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}
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/**
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* uniphier_cache_maint_common - run a queue operation
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*
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* @start: start address of range operation (don't care for "all" operation)
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* @size: data size of range operation (don't care for "all" operation)
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* @ways: target ways (don't care for operations other than pre-fetch, touch
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* @operation: flags to specify the desired cache operation
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*/
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static void uniphier_cache_maint_common(u32 start, u32 size, u32 ways,
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u32 operation)
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{
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/* clear the complete notification flag */
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writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
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do {
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/* set cache operation */
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writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM);
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/* set address range if needed */
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if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) {
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writel(start, UNIPHIER_SSCOQAD);
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writel(size, UNIPHIER_SSCOQSZ);
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}
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/* set target ways if needed */
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if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation)))
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writel(ways, UNIPHIER_SSCOQWN);
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} while (unlikely(readl(UNIPHIER_SSCOPPQSEF) &
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(UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE)));
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/* wait until the operation is completed */
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while (likely(readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF))
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cpu_relax();
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}
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static void uniphier_cache_maint_all(u32 operation)
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{
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uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation);
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uniphier_cache_sync();
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}
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static void uniphier_cache_maint_range(u32 start, u32 end, u32 ways,
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u32 operation)
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{
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u32 size;
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/*
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* If the start address is not aligned,
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* perform a cache operation for the first cache-line
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*/
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start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1);
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size = end - start;
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if (unlikely(size >= (u32)(-UNIPHIER_SSC_LINE_SIZE))) {
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/* this means cache operation for all range */
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uniphier_cache_maint_all(operation);
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return;
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}
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/*
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* If the end address is not aligned,
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* perform a cache operation for the last cache-line
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*/
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size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE);
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while (size) {
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u32 chunk_size = min_t(u32, size, UNIPHIER_SSC_RANGE_OP_MAX_SIZE);
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uniphier_cache_maint_common(start, chunk_size, ways,
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UNIPHIER_SSCOQM_S_RANGE | operation);
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start += chunk_size;
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size -= chunk_size;
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}
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uniphier_cache_sync();
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}
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void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways)
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{
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uniphier_cache_maint_range(start, end, ways,
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UNIPHIER_SSCOQM_TID_WAY |
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UNIPHIER_SSCOQM_CM_PREFETCH);
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}
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void uniphier_cache_touch_range(u32 start, u32 end, u32 ways)
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{
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uniphier_cache_maint_range(start, end, ways,
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UNIPHIER_SSCOQM_TID_WAY |
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UNIPHIER_SSCOQM_CM_TOUCH);
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}
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void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways)
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{
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uniphier_cache_maint_range(start, end, ways,
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UNIPHIER_SSCOQM_TID_WAY |
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UNIPHIER_SSCOQM_CM_TOUCH_ZERO);
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}
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void uniphier_cache_inv_way(u32 ways)
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{
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uniphier_cache_maint_common(0, 0, ways,
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UNIPHIER_SSCOQM_S_WAY |
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UNIPHIER_SSCOQM_CM_INV);
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}
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void uniphier_cache_set_active_ways(int cpu, u32 active_ways)
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{
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void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
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switch (readl(UNIPHIER_SSCID)) { /* revision */
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case 0x12: /* LD4 */
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case 0x16: /* sld8 */
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base = (void __iomem *)UNIPHIER_SSCC + 0x840;
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break;
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default:
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base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
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break;
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}
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writel(active_ways, base + 4 * cpu);
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}
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static void uniphier_cache_endisable(int enable)
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{
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u32 tmp;
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tmp = readl(UNIPHIER_SSCC);
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if (enable)
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tmp |= UNIPHIER_SSCC_ON;
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else
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tmp &= ~UNIPHIER_SSCC_ON;
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writel(tmp, UNIPHIER_SSCC);
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}
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void uniphier_cache_enable(void)
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{
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uniphier_cache_endisable(1);
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}
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void uniphier_cache_disable(void)
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{
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uniphier_cache_endisable(0);
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}
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#ifdef CONFIG_CACHE_UNIPHIER
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void v7_outer_cache_flush_all(void)
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{
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uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
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}
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void v7_outer_cache_inval_all(void)
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{
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uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
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}
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void v7_outer_cache_flush_range(u32 start, u32 end)
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{
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uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_FLUSH);
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}
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void v7_outer_cache_inval_range(u32 start, u32 end)
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{
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if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) {
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start &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
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uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, 0,
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UNIPHIER_SSCOQM_CM_FLUSH);
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start += UNIPHIER_SSC_LINE_SIZE;
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}
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if (start >= end) {
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uniphier_cache_sync();
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return;
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}
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if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) {
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end &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
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uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, 0,
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UNIPHIER_SSCOQM_CM_FLUSH);
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}
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if (start >= end) {
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uniphier_cache_sync();
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return;
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}
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uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_INV);
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}
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void v7_outer_cache_enable(void)
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{
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uniphier_cache_set_active_ways(0, U32_MAX); /* activate all ways */
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uniphier_cache_enable();
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}
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void v7_outer_cache_disable(void)
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{
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uniphier_cache_disable();
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}
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#endif
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void enable_caches(void)
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{
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dcache_enable();
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}
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