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![Jean-Jacques Hiblot](/assets/img/avatar_default.png)
The DRA7 platforms requires that the dtb used in the SPL really matches the platform to have the best MMC performances. To detect the board type/version an I2C EEPROM is read. This requires that DM is initialized before the detection. As a consequence we must reset the DM after the board detection is a new dtb would better match the platform. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
351 lines
6.9 KiB
C
351 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* Common functions for OMAP4/5 based boards
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <fdtdec.h>
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#include <spl.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/sizes.h>
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#include <asm/emif.h>
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#include <asm/omap_common.h>
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#include <linux/compiler.h>
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#include <asm/system.h>
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#include <dm/root.h>
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DECLARE_GLOBAL_DATA_PTR;
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void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
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{
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int i;
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struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
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for (i = 0; i < size; i++, pad++)
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writew(pad->val, base + pad->offset);
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}
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static void set_mux_conf_regs(void)
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{
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switch (omap_hw_init_context()) {
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case OMAP_INIT_CONTEXT_SPL:
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set_muxconf_regs();
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break;
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case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
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break;
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case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
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case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
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set_muxconf_regs();
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break;
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}
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}
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u32 cortex_rev(void)
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{
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unsigned int rev;
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/* Read Main ID Register (MIDR) */
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asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
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return rev;
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}
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static void omap_rev_string(void)
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{
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u32 omap_rev = omap_revision();
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u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
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u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
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u32 major_rev = (omap_rev & 0x00000F00) >> 8;
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u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
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const char *sec_s, *package = NULL;
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switch (get_device_type()) {
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case TST_DEVICE:
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sec_s = "TST";
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break;
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case EMU_DEVICE:
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sec_s = "EMU";
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break;
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case HS_DEVICE:
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sec_s = "HS";
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break;
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case GP_DEVICE:
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sec_s = "GP";
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break;
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default:
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sec_s = "?";
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}
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#if defined(CONFIG_DRA7XX)
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if (is_dra76x()) {
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switch (omap_rev & 0xF) {
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case DRA762_ABZ_PACKAGE:
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package = "ABZ";
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break;
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case DRA762_ACD_PACKAGE:
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default:
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package = "ACD";
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break;
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}
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}
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#endif
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if (soc_variant)
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printf("OMAP");
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else
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printf("DRA");
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printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev);
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if (package)
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printf(" %s package\n", package);
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else
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puts("\n");
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}
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#ifdef CONFIG_SPL_BUILD
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void spl_display_print(void)
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{
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omap_rev_string();
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}
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#endif
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void __weak srcomp_enable(void)
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{
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}
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/**
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* do_board_detect() - Detect board description
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*
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* Function to detect board description. This is expected to be
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* overridden in the SoC family board file where desired.
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*/
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void __weak do_board_detect(void)
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{
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}
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/**
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* vcores_init() - Assign omap_vcores based on board
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*
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* Function to pick the vcores based on board. This is expected to be
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* overridden in the SoC family board file where desired.
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*/
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void __weak vcores_init(void)
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{
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}
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void s_init(void)
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{
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}
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/**
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* init_package_revision() - Initialize package revision
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*
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* Function to get the pacakage information. This is expected to be
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* overridden in the SoC family file where desired.
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*/
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void __weak init_package_revision(void)
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{
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}
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/**
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* early_system_init - Does Early system initialization.
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*
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* Does early system init of watchdog, muxing, andclocks
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* Watchdog disable is done always. For the rest what gets done
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* depends on the boot mode in which this function is executed when
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* 1. SPL running from SRAM
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* 2. U-Boot running from FLASH
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* 3. U-Boot loaded to SDRAM by SPL
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* 4. U-Boot loaded to SDRAM by ROM code using the
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* Configuration Header feature
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* Please have a look at the respective functions to see what gets
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* done in each of these cases
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* This function is called with SRAM stack.
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*/
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void early_system_init(void)
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{
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
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int ret;
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int rescan;
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#endif
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init_omap_revision();
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hw_data_init();
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init_package_revision();
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#ifdef CONFIG_SPL_BUILD
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if (warm_reset())
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force_emif_self_refresh();
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#endif
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watchdog_init();
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set_mux_conf_regs();
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#ifdef CONFIG_SPL_BUILD
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srcomp_enable();
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do_io_settings();
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#endif
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setup_early_clocks();
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#ifdef CONFIG_SPL_BUILD
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/*
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* Save the boot parameters passed from romcode.
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* We cannot delay the saving further than this,
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* to prevent overwrites.
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*/
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save_omap_boot_params();
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spl_early_init();
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#endif
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do_board_detect();
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
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/*
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* Board detection has been done.
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* Let us see if another dtb wouldn't be a better match
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* for our board
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*/
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ret = fdtdec_resetup(&rescan);
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if (!ret && rescan) {
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dm_uninit();
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dm_init_and_scan(true);
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}
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#endif
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vcores_init();
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#ifdef CONFIG_DEBUG_UART_OMAP
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debug_uart_init();
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#endif
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prcm_init();
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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early_system_init();
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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board_early_init_f();
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#endif
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/* For regular u-boot sdram_init() is called from dram_init() */
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sdram_init();
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gd->ram_size = omap_sdram_size();
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}
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#endif
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int arch_cpu_init_dm(void)
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{
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early_system_init();
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return 0;
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}
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/*
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* Routine: wait_for_command_complete
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* Description: Wait for posting to finish on watchdog
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*/
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void wait_for_command_complete(struct watchdog *wd_base)
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{
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int pending = 1;
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do {
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pending = readl(&wd_base->wwps);
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} while (pending);
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}
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/*
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* Routine: watchdog_init
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* Description: Shut down watch dogs
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*/
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void watchdog_init(void)
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{
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struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
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writel(WD_UNLOCK1, &wd2_base->wspr);
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wait_for_command_complete(wd2_base);
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writel(WD_UNLOCK2, &wd2_base->wspr);
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}
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/*
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* This function finds the SDRAM size available in the system
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* based on DMM section configurations
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* This is needed because the size of memory installed may be
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* different on different versions of the board
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*/
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u32 omap_sdram_size(void)
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{
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u32 section, i, valid;
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u64 sdram_start = 0, sdram_end = 0, addr,
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size, total_size = 0, trap_size = 0, trap_start = 0;
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for (i = 0; i < 4; i++) {
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section = __raw_readl(DMM_BASE + i*4);
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valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
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(EMIF_SDRC_ADDRSPC_SHIFT);
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addr = section & EMIF_SYS_ADDR_MASK;
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/* See if the address is valid */
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if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
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(addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
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size = ((section & EMIF_SYS_SIZE_MASK) >>
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EMIF_SYS_SIZE_SHIFT);
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size = 1 << size;
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size *= SZ_16M;
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if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
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if (!sdram_start || (addr < sdram_start))
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sdram_start = addr;
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if (!sdram_end || ((addr + size) > sdram_end))
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sdram_end = addr + size;
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} else {
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trap_size = size;
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trap_start = addr;
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}
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}
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}
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if ((trap_start >= sdram_start) && (trap_start < sdram_end))
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total_size = (sdram_end - sdram_start) - (trap_size);
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else
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total_size = sdram_end - sdram_start;
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return total_size;
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}
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/*
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* Routine: dram_init
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* Description: sets uboots idea of sdram size
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*/
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int dram_init(void)
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{
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sdram_init();
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gd->ram_size = omap_sdram_size();
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return 0;
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}
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/*
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* Print board information
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*/
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int checkboard(void)
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{
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puts(sysinfo.board_string);
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return 0;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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/*
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* Print CPU information
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*/
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int print_cpuinfo(void)
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{
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puts("CPU : ");
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omap_rev_string();
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return 0;
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}
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#endif
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