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https://github.com/brain-hackers/u-boot-brain
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![Paul Kocialkowski](/assets/img/avatar_default.png)
Some generic PX30 SoMs found in the wild use UART3 as their debug output instead of UART2 (used for MMC) and UART5. Make it possible to use UART3 as early debug output, with the associated clock and pinmux configuration. Two sets of output pins are supported (M0/M1). Future users should also note that the pinmux default in the dts is to use the M1 pins while the Kconfig option takes M0 as a default. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
452 lines
11 KiB
C
452 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _ASM_ARCH_CRU_PX30_H
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#define _ASM_ARCH_CRU_PX30_H
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#include <common.h>
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (1200 * MHz)
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#define NPLL_HZ (1188 * MHz)
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#define ACLK_BUS_HZ (200 * MHz)
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#define HCLK_BUS_HZ (150 * MHz)
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#define PCLK_BUS_HZ (100 * MHz)
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#define ACLK_PERI_HZ (200 * MHz)
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#define HCLK_PERI_HZ (150 * MHz)
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#define PCLK_PMU_HZ (100 * MHz)
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/* PX30 pll id */
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enum px30_pll_id {
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APLL,
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DPLL,
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CPLL,
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NPLL,
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GPLL,
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PLL_COUNT,
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};
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struct px30_clk_priv {
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struct px30_cru *cru;
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ulong gpll_hz;
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};
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struct px30_pmuclk_priv {
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struct px30_pmucru *pmucru;
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ulong gpll_hz;
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};
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struct px30_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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};
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struct px30_cru {
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struct px30_pll pll[4];
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unsigned int reserved1[8];
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unsigned int mode;
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unsigned int misc;
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unsigned int reserved2[2];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int reserved3[7];
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unsigned int hwffc_con0;
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unsigned int reserved4;
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unsigned int hwffc_th;
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unsigned int hwffc_intst;
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unsigned int apll_con0_s;
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unsigned int apll_con1_s;
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unsigned int clksel_con0_s;
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unsigned int reserved5;
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unsigned int clksel_con[60];
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unsigned int reserved6[4];
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unsigned int clkgate_con[18];
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unsigned int reserved7[(0x280 - 0x244) / 4 - 1];
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unsigned int ssgtbl[32];
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unsigned int softrst_con[12];
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unsigned int reserved8[(0x380 - 0x32c) / 4 - 1];
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unsigned int sdmmc_con[2];
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unsigned int sdio_con[2];
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unsigned int emmc_con[2];
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unsigned int reserved9[(0x400 - 0x394) / 4 - 1];
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unsigned int autocs_con[8];
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};
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check_member(px30_cru, autocs_con[7], 0x41c);
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struct px30_pmucru {
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struct px30_pll pll;
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unsigned int pmu_mode;
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unsigned int reserved1[7];
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unsigned int pmu_clksel_con[6];
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unsigned int reserved2[10];
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unsigned int pmu_clkgate_con[2];
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unsigned int reserved3[14];
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unsigned int pmu_autocs_con[2];
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};
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check_member(px30_pmucru, pmu_autocs_con[1], 0xc4);
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struct pll_rate_table {
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unsigned long rate;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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struct cpu_rate_table {
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unsigned long rate;
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unsigned int aclk_div;
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unsigned int pclk_div;
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};
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enum {
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/* PLLCON0*/
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PLL_BP_SHIFT = 15,
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PLL_POSTDIV1_SHIFT = 12,
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PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
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PLL_FBDIV_SHIFT = 0,
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PLL_FBDIV_MASK = 0xfff,
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/* PLLCON1 */
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PLL_PDSEL_SHIFT = 15,
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PLL_PD1_SHIFT = 14,
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PLL_PD_SHIFT = 13,
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PLL_PD_MASK = 1 << PLL_PD_SHIFT,
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PLL_DSMPD_SHIFT = 12,
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PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
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PLL_LOCK_STATUS_SHIFT = 10,
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PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
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PLL_POSTDIV2_SHIFT = 6,
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PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
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PLL_REFDIV_SHIFT = 0,
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PLL_REFDIV_MASK = 0x3f,
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/* PLLCON2 */
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PLL_FOUT4PHASEPD_SHIFT = 27,
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PLL_FOUTVCOPD_SHIFT = 26,
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PLL_FOUTPOSTDIVPD_SHIFT = 25,
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PLL_DACPD_SHIFT = 24,
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PLL_FRAC_DIV = 0xffffff,
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/* CRU_MODE */
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PLLMUX_FROM_XIN24M = 0,
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PLLMUX_FROM_PLL,
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PLLMUX_FROM_RTC32K,
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USBPHY480M_MODE_SHIFT = 8,
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USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
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NPLL_MODE_SHIFT = 6,
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NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT,
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DPLL_MODE_SHIFT = 4,
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DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
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CPLL_MODE_SHIFT = 2,
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CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT,
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APLL_MODE_SHIFT = 0,
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APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
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/* CRU_CLK_SEL0_CON */
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CORE_ACLK_DIV_SHIFT = 12,
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CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT,
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CORE_DBG_DIV_SHIFT = 8,
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CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 7,
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CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_GPLL,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
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/* CRU_CLK_SEL3_CON */
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ACLK_VO_PLL_SHIFT = 6,
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ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT,
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ACLK_VO_SEL_GPLL = 0,
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ACLK_VO_SEL_CPLL,
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ACLK_VO_SEL_NPLL,
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ACLK_VO_DIV_SHIFT = 0,
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ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT,
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/* CRU_CLK_SEL5_CON */
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DCLK_VOPB_SEL_SHIFT = 14,
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DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT,
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DCLK_VOPB_SEL_DIVOUT = 0,
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DCLK_VOPB_SEL_FRACOUT,
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DCLK_VOPB_SEL_24M,
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DCLK_VOPB_PLL_SEL_SHIFT = 11,
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DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT,
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DCLK_VOPB_PLL_SEL_CPLL = 0,
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DCLK_VOPB_PLL_SEL_NPLL,
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DCLK_VOPB_DIV_SHIFT = 0,
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DCLK_VOPB_DIV_MASK = 0xff,
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/* CRU_CLK_SEL8_CON */
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DCLK_VOPL_SEL_SHIFT = 14,
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DCLK_VOPL_SEL_MASK = 0x3 << DCLK_VOPL_SEL_SHIFT,
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DCLK_VOPL_SEL_DIVOUT = 0,
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DCLK_VOPL_SEL_FRACOUT,
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DCLK_VOPL_SEL_24M,
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DCLK_VOPL_PLL_SEL_SHIFT = 11,
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DCLK_VOPL_PLL_SEL_MASK = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT,
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DCLK_VOPL_PLL_SEL_NPLL = 0,
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DCLK_VOPL_PLL_SEL_CPLL,
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DCLK_VOPL_DIV_SHIFT = 0,
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DCLK_VOPL_DIV_MASK = 0xff,
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/* CRU_CLK_SEL14_CON */
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PERI_PLL_SEL_SHIFT = 15,
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PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
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PERI_PLL_GPLL = 0,
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PERI_PLL_CPLL,
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PERI_HCLK_DIV_SHIFT = 8,
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PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
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PERI_ACLK_DIV_SHIFT = 0,
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PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
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/* CRU_CLKSEL15_CON */
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NANDC_CLK_SEL_SHIFT = 15,
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NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT,
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NANDC_CLK_SEL_NANDC = 0,
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NANDC_CLK_SEL_NANDC_DIV50,
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NANDC_DIV50_SHIFT = 8,
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NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT,
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NANDC_PLL_SHIFT = 6,
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NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT,
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NANDC_SEL_GPLL = 0,
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NANDC_SEL_CPLL,
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NANDC_SEL_NPLL,
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NANDC_DIV_SHIFT = 0,
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NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT,
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/* CRU_CLKSEL20_CON */
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EMMC_PLL_SHIFT = 14,
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EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
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EMMC_SEL_GPLL = 0,
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EMMC_SEL_CPLL,
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EMMC_SEL_NPLL,
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EMMC_SEL_24M,
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EMMC_DIV_SHIFT = 0,
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EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
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/* CRU_CLKSEL21_CON */
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EMMC_CLK_SEL_SHIFT = 15,
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EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
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EMMC_CLK_SEL_EMMC = 0,
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EMMC_CLK_SEL_EMMC_DIV50,
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EMMC_DIV50_SHIFT = 0,
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EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT,
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/* CRU_CLKSEL22_CON */
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GMAC_PLL_SEL_SHIFT = 14,
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GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT,
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GMAC_PLL_SEL_GPLL = 0,
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GMAC_PLL_SEL_CPLL,
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GMAC_PLL_SEL_NPLL,
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CLK_GMAC_DIV_SHIFT = 8,
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CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT,
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SFC_PLL_SEL_SHIFT = 7,
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SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
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SFC_DIV_CON_SHIFT = 0,
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SFC_DIV_CON_MASK = 0x7f,
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/* CRU_CLK_SEL23_CON */
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BUS_PLL_SEL_SHIFT = 15,
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BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT,
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BUS_PLL_SEL_GPLL = 0,
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BUS_PLL_SEL_CPLL,
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BUS_ACLK_DIV_SHIFT = 8,
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BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
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RMII_CLK_SEL_SHIFT = 7,
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RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT,
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RMII_CLK_SEL_10M = 0,
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RMII_CLK_SEL_100M,
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RMII_EXTCLK_SEL_SHIFT = 6,
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RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT,
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RMII_EXTCLK_SEL_INT = 0,
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RMII_EXTCLK_SEL_EXT,
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PCLK_GMAC_DIV_SHIFT = 0,
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PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT,
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/* CRU_CLK_SEL24_CON */
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BUS_PCLK_DIV_SHIFT = 8,
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BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT,
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BUS_HCLK_DIV_SHIFT = 0,
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BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
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/* CRU_CLK_SEL25_CON */
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CRYPTO_APK_SEL_SHIFT = 14,
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CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
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CRYPTO_PLL_SEL_GPLL = 0,
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CRYPTO_PLL_SEL_CPLL,
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CRYPTO_PLL_SEL_NPLL = 0,
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CRYPTO_APK_DIV_SHIFT = 8,
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CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
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CRYPTO_PLL_SEL_SHIFT = 6,
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CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
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CRYPTO_DIV_SHIFT = 0,
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CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
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/* CRU_CLK_SEL30_CON */
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CLK_I2S1_DIV_CON_MASK = 0x7f,
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CLK_I2S1_PLL_SEL_MASK = 0X1 << 8,
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CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8,
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CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8,
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CLK_I2S1_SEL_MASK = 0x3 << 10,
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CLK_I2S1_SEL_I2S1 = 0x0 << 10,
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CLK_I2S1_SEL_FRAC = 0x1 << 10,
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CLK_I2S1_SEL_MCLK_IN = 0x2 << 10,
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CLK_I2S1_SEL_OSC = 0x3 << 10,
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CLK_I2S1_OUT_SEL_MASK = 0x1 << 15,
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CLK_I2S1_OUT_SEL_I2S1 = 0x0 << 15,
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CLK_I2S1_OUT_SEL_OSC = 0x1 << 15,
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/* CRU_CLK_SEL31_CON */
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CLK_I2S1_FRAC_NUMERATOR_SHIFT = 16,
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CLK_I2S1_FRAC_NUMERATOR_MASK = 0xffff << 16,
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CLK_I2S1_FRAC_DENOMINATOR_SHIFT = 0,
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CLK_I2S1_FRAC_DENOMINATOR_MASK = 0xffff,
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/* CRU_CLK_SEL34_CON */
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UART1_PLL_SEL_SHIFT = 14,
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UART1_PLL_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
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UART1_PLL_SEL_GPLL = 0,
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UART1_PLL_SEL_24M,
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UART1_PLL_SEL_480M,
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UART1_PLL_SEL_NPLL,
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UART1_DIV_CON_SHIFT = 0,
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UART1_DIV_CON_MASK = 0x1f << UART1_DIV_CON_SHIFT,
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/* CRU_CLK_SEL35_CON */
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UART1_CLK_SEL_SHIFT = 14,
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UART1_CLK_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
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UART1_CLK_SEL_UART1 = 0,
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UART1_CLK_SEL_UART1_NP5,
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UART1_CLK_SEL_UART1_FRAC,
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UART1_DIVNP5_SHIFT = 0,
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UART1_DIVNP5_MASK = 0x1f << UART1_DIVNP5_SHIFT,
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/* CRU_CLK_SEL37_CON */
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UART2_PLL_SEL_SHIFT = 14,
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UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
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UART2_PLL_SEL_GPLL = 0,
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UART2_PLL_SEL_24M,
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UART2_PLL_SEL_480M,
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UART2_PLL_SEL_NPLL,
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UART2_DIV_CON_SHIFT = 0,
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UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT,
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/* CRU_CLK_SEL38_CON */
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UART2_CLK_SEL_SHIFT = 14,
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UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
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UART2_CLK_SEL_UART2 = 0,
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UART2_CLK_SEL_UART2_NP5,
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UART2_CLK_SEL_UART2_FRAC,
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UART2_DIVNP5_SHIFT = 0,
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UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT,
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/* CRU_CLK_SEL40_CON */
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UART3_PLL_SEL_SHIFT = 14,
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UART3_PLL_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
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UART3_PLL_SEL_GPLL = 0,
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UART3_PLL_SEL_24M,
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UART3_PLL_SEL_480M,
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UART3_PLL_SEL_NPLL,
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UART3_DIV_CON_SHIFT = 0,
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UART3_DIV_CON_MASK = 0x1f << UART3_DIV_CON_SHIFT,
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/* CRU_CLK_SEL41_CON */
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UART3_CLK_SEL_SHIFT = 14,
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UART3_CLK_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
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UART3_CLK_SEL_UART3 = 0,
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UART3_CLK_SEL_UART3_NP5,
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UART3_CLK_SEL_UART3_FRAC,
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UART3_DIVNP5_SHIFT = 0,
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UART3_DIVNP5_MASK = 0x1f << UART3_DIVNP5_SHIFT,
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/* CRU_CLK_SEL46_CON */
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UART5_PLL_SEL_SHIFT = 14,
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UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
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UART5_PLL_SEL_GPLL = 0,
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UART5_PLL_SEL_24M,
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UART5_PLL_SEL_480M,
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UART5_PLL_SEL_NPLL,
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UART5_DIV_CON_SHIFT = 0,
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UART5_DIV_CON_MASK = 0x1f << UART5_DIV_CON_SHIFT,
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/* CRU_CLK_SEL47_CON */
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UART5_CLK_SEL_SHIFT = 14,
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UART5_CLK_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
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UART5_CLK_SEL_UART5 = 0,
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UART5_CLK_SEL_UART5_NP5,
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UART5_CLK_SEL_UART5_FRAC,
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UART5_DIVNP5_SHIFT = 0,
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UART5_DIVNP5_MASK = 0x1f << UART5_DIVNP5_SHIFT,
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/* CRU_CLK_SEL49_CON */
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CLK_I2C_PLL_SEL_GPLL = 0,
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CLK_I2C_PLL_SEL_24M,
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CLK_I2C_DIV_CON_MASK = 0x7f,
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CLK_I2C_PLL_SEL_MASK = 1,
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CLK_I2C1_PLL_SEL_SHIFT = 15,
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CLK_I2C1_DIV_CON_SHIFT = 8,
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CLK_I2C0_PLL_SEL_SHIFT = 7,
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CLK_I2C0_DIV_CON_SHIFT = 0,
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/* CRU_CLK_SEL50_CON */
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CLK_I2C3_PLL_SEL_SHIFT = 15,
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CLK_I2C3_DIV_CON_SHIFT = 8,
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CLK_I2C2_PLL_SEL_SHIFT = 7,
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CLK_I2C2_DIV_CON_SHIFT = 0,
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/* CRU_CLK_SEL52_CON */
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CLK_PWM_PLL_SEL_GPLL = 0,
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CLK_PWM_PLL_SEL_24M,
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CLK_PWM_DIV_CON_MASK = 0x7f,
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CLK_PWM_PLL_SEL_MASK = 1,
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CLK_PWM1_PLL_SEL_SHIFT = 15,
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CLK_PWM1_DIV_CON_SHIFT = 8,
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CLK_PWM0_PLL_SEL_SHIFT = 7,
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CLK_PWM0_DIV_CON_SHIFT = 0,
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/* CRU_CLK_SEL53_CON */
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CLK_SPI_PLL_SEL_GPLL = 0,
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CLK_SPI_PLL_SEL_24M,
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CLK_SPI_DIV_CON_MASK = 0x7f,
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CLK_SPI_PLL_SEL_MASK = 1,
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CLK_SPI1_PLL_SEL_SHIFT = 15,
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CLK_SPI1_DIV_CON_SHIFT = 8,
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CLK_SPI0_PLL_SEL_SHIFT = 7,
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CLK_SPI0_DIV_CON_SHIFT = 0,
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/* CRU_CLK_SEL55_CON */
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CLK_SARADC_DIV_CON_SHIFT = 0,
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CLK_SARADC_DIV_CON_MASK = 0x7ff,
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|
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/* CRU_CLK_GATE10_CON */
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CLK_I2S1_OUT_MCLK_PAD_MASK = 0x1 << 9,
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CLK_I2S1_OUT_MCLK_PAD_ENABLE = 0x1 << 9,
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CLK_I2S1_OUT_MCLK_PAD_DISABLE = 0x0 << 9,
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/* CRU_PMU_MODE */
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GPLL_MODE_SHIFT = 0,
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GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
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/* CRU_PMU_CLK_SEL0_CON */
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CLK_PMU_PCLK_DIV_SHIFT = 0,
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CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT,
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};
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#endif
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