mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
d32a874b9b
Limit the rate of h/w watch-dog triggering on the LWMON5 board by the CONFIG_WD_MAX_RATE value. Note that an earlier version of this patch which used microseconds instead of ticks dis not work. The problem was that we used usec2ticks() to convert microseconds into ticks. usec2ticks() uses get_tbclk(), which in turn calls get_sys_info(). It turns out that this function does a lot of prolonged operations (like divisions) which take too much time so we do not trigger the watchdog in time, and it resets the system. Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
181 lines
5.1 KiB
C
181 lines
5.1 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#include "asm/types.h"
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/*
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* The following data structure is placed in some memory wich is
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* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
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* some locked parts of the data cache) to allow for a minimum set of
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* global variables during system initialization (until we have set
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* up the memory controller so that we can use RAM).
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*
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* Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
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*/
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typedef struct global_data {
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bd_t *bd;
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unsigned long flags;
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unsigned long baudrate;
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unsigned long cpu_clk; /* CPU clock in Hz! */
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unsigned long bus_clk;
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#if defined(CONFIG_CPM2)
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/* There are many clocks on the MPC8260 - see page 9-5 */
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unsigned long vco_out;
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unsigned long cpm_clk;
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unsigned long scc_clk;
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unsigned long brg_clk;
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#endif
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#if defined(CONFIG_MPC7448HPC2)
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unsigned long mem_clk;
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#endif
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#if defined(CONFIG_MPC83XX)
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/* There are other clocks in the MPC83XX */
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u32 csb_clk;
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#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
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u32 tsec1_clk;
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u32 tsec2_clk;
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u32 usbdr_clk;
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#endif
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#if defined (CONFIG_MPC834X)
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u32 usbmph_clk;
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#endif /* CONFIG_MPC834X */
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#if defined(CONFIG_MPC8315)
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u32 tdm_clk;
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#endif
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#if defined(CONFIG_MPC837X)
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u32 sdhc_clk;
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#endif
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u32 core_clk;
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u32 enc_clk;
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u32 lbiu_clk;
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u32 lclk_clk;
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u32 ddr_clk;
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u32 pci_clk;
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#if defined(CONFIG_MPC837X)
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u32 pciexp1_clk;
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u32 pciexp2_clk;
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#endif
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#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
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u32 sata_clk;
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#endif
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#if defined(CONFIG_MPC8360)
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u32 ddr_sec_clk;
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#endif /* CONFIG_MPC8360 */
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#endif
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#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
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u32 i2c1_clk;
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u32 i2c2_clk;
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#endif
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#if defined(CONFIG_QE)
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u32 qe_clk;
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u32 brg_clk;
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uint mp_alloc_base;
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uint mp_alloc_top;
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#endif /* CONFIG_QE */
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#if defined(CONFIG_MPC5xxx)
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unsigned long ipb_clk;
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unsigned long pci_clk;
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#endif
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#if defined(CONFIG_MPC512X)
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u32 ips_clk;
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u32 csb_clk;
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u32 pci_clk;
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#endif /* CONFIG_MPC512X */
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#if defined(CONFIG_MPC8220)
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unsigned long bExtUart;
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unsigned long inp_clk;
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unsigned long pci_clk;
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unsigned long vco_clk;
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unsigned long pev_clk;
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unsigned long flb_clk;
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#endif
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unsigned long ram_size; /* RAM size */
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unsigned long reloc_off; /* Relocation Offset */
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unsigned long reset_status; /* reset status register at boot */
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unsigned long env_addr; /* Address of Environment struct */
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unsigned long env_valid; /* Checksum of Environment valid? */
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unsigned long have_console; /* serial_init() was called */
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#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2)
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unsigned int dp_alloc_base;
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unsigned int dp_alloc_top;
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#endif
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#if defined(CONFIG_4xx)
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u32 uart_clk;
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#endif /* CONFIG_4xx */
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#if defined(CFG_GT_6426x)
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unsigned int mirror_hack[16];
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#endif
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#if defined(CONFIG_A3000) || \
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defined(CONFIG_HIDDEN_DRAGON) || \
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defined(CONFIG_MUSENKI) || \
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defined(CONFIG_SANDPOINT)
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void * console_addr;
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#endif
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#ifdef CONFIG_AMIGAONEG3SE
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unsigned long relocaddr; /* Start address of U-Boot in RAM */
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#endif
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#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
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unsigned long fb_base; /* Base address of framebuffer memory */
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#endif
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#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
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unsigned long post_log_word; /* Record POST activities */
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unsigned long post_init_f_time; /* When post_init_f started */
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#endif
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#ifdef CONFIG_BOARD_TYPES
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unsigned long board_type;
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#endif
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#ifdef CONFIG_MODEM_SUPPORT
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unsigned long do_mdm_init;
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unsigned long be_quiet;
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#endif
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#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
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unsigned long kbd_status;
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#endif
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#if defined(CONFIG_WD_MAX_RATE)
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unsigned long long wdt_last; /* trace watch-dog triggering rate */
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#endif
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void **jt; /* jump table */
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} gd_t;
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/*
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* Global Data Flags
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*/
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#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
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#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
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#define GD_FLG_SILENT 0x00004 /* Silent mode */
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#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
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#if 1
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#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
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#else /* We could use plain global data, but the resulting code is bigger */
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#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
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#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
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gd_t *gd
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#endif
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#endif /* __ASM_GBL_DATA_H */
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