mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 13:23:20 +09:00
![Thierry Reding](/assets/img/avatar_default.png)
A subsequent patch will enable the use of the architected timer on ARMv8. Doing so implies that udelay() will be backed by this timer implementation, and hence the architected timer must be ready when udelay() is first called. The first time udelay() is used is while resetting the debug UART, which happens very early. Make sure that arch_timer_init() is called before that. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
299 lines
6.1 KiB
C
299 lines
6.1 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <ns16550.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#ifdef CONFIG_LCD
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#include <asm/arch/display.h>
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#endif
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pmu.h>
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#ifdef CONFIG_PWM_TEGRA
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#include <asm/arch/pwm.h>
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#endif
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/board.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/sys_proto.h>
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#include <asm/arch-tegra/uart.h>
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#include <asm/arch-tegra/warmboot.h>
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#ifdef CONFIG_TEGRA_CLOCK_SCALING
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#include <asm/arch/emc.h>
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#endif
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#ifdef CONFIG_USB_EHCI_TEGRA
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#include <asm/arch-tegra/usb.h>
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#include <usb.h>
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#endif
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#ifdef CONFIG_TEGRA_MMC
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#include <asm/arch-tegra/tegra_mmc.h>
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#include <asm/arch-tegra/mmc.h>
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#endif
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#include <asm/arch-tegra/xusb-padctl.h>
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#include <power/as3722.h>
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#include <i2c.h>
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#include <spi.h>
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#include "emc.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
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U_BOOT_DEVICE(tegra_gpios) = {
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"gpio_tegra"
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};
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#endif
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__weak void pinmux_init(void) {}
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__weak void pin_mux_usb(void) {}
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__weak void pin_mux_spi(void) {}
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__weak void gpio_early_init_uart(void) {}
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__weak void pin_mux_display(void) {}
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#if defined(CONFIG_TEGRA_NAND)
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__weak void pin_mux_nand(void)
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{
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funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
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}
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#endif
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/*
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* Routine: power_det_init
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* Description: turn off power detects
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*/
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static void power_det_init(void)
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{
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#if defined(CONFIG_TEGRA20)
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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/* turn off power detects */
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writel(0, &pmc->pmc_pwr_det_latch);
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writel(0, &pmc->pmc_pwr_det);
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#endif
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}
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__weak int tegra_board_id(void)
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{
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return -1;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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int board_id = tegra_board_id();
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printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
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if (board_id != -1)
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printf(", ID: %d\n", board_id);
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printf("\n");
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return 0;
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}
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#endif /* CONFIG_DISPLAY_BOARDINFO */
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__weak int tegra_lcd_pmic_init(int board_it)
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{
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return 0;
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}
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__weak int nvidia_board_init(void)
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{
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return 0;
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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__maybe_unused int err;
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__maybe_unused int board_id;
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/* Do clocks and UART first so that printf() works */
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clock_init();
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clock_verify();
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#ifdef CONFIG_TEGRA_SPI
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pin_mux_spi();
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#endif
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#ifdef CONFIG_PWM_TEGRA
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if (pwm_init(gd->fdt_blob))
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debug("%s: Failed to init pwm\n", __func__);
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#endif
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#ifdef CONFIG_LCD
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pin_mux_display();
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tegra_lcd_check_next_stage(gd->fdt_blob, 0);
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#endif
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/* boot param addr */
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gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
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power_det_init();
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#ifdef CONFIG_SYS_I2C_TEGRA
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# ifdef CONFIG_TEGRA_PMU
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if (pmu_set_nominal())
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debug("Failed to select nominal voltages\n");
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# ifdef CONFIG_TEGRA_CLOCK_SCALING
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err = board_emc_init();
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if (err)
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debug("Memory controller init failed: %d\n", err);
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# endif
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# endif /* CONFIG_TEGRA_PMU */
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#ifdef CONFIG_AS3722_POWER
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err = as3722_init(NULL);
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if (err && err != -ENODEV)
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return err;
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#endif
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#endif /* CONFIG_SYS_I2C_TEGRA */
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#ifdef CONFIG_USB_EHCI_TEGRA
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pin_mux_usb();
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#endif
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#ifdef CONFIG_LCD
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board_id = tegra_board_id();
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err = tegra_lcd_pmic_init(board_id);
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if (err)
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return err;
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tegra_lcd_check_next_stage(gd->fdt_blob, 0);
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#endif
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#ifdef CONFIG_TEGRA_NAND
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pin_mux_nand();
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#endif
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tegra_xusb_padctl_init(gd->fdt_blob);
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#ifdef CONFIG_TEGRA_LP0
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/* save Sdram params to PMC 2, 4, and 24 for WB0 */
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warmboot_save_sdram_params();
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/* prepare the WB code to LP0 location */
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warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
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#endif
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return nvidia_board_init();
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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static void __gpio_early_init(void)
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{
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}
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void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
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int board_early_init_f(void)
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{
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/* Do any special system timer/TSC setup */
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#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
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if (!tegra_cpu_is_non_secure())
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#endif
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arch_timer_init();
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pinmux_init();
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board_init_uart_f();
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/* Initialize periph GPIOs */
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gpio_early_init();
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gpio_early_init_uart();
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#ifdef CONFIG_LCD
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tegra_lcd_early_init(gd->fdt_blob);
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#endif
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return 0;
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}
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#endif /* EARLY_INIT */
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int board_late_init(void)
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{
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#ifdef CONFIG_LCD
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/* Make sure we finish initing the LCD */
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tegra_lcd_check_next_stage(gd->fdt_blob, 1);
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#endif
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#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
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if (tegra_cpu_is_non_secure()) {
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printf("CPU is in NS mode\n");
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setenv("cpu_ns_mode", "1");
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} else {
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setenv("cpu_ns_mode", "");
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}
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#endif
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return 0;
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}
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#if defined(CONFIG_TEGRA_MMC)
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__weak void pin_mux_mmc(void)
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{
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}
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/* this is a weak define that we are overriding */
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int board_mmc_init(bd_t *bd)
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{
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debug("%s called\n", __func__);
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/* Enable muxes, etc. for SDMMC controllers */
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pin_mux_mmc();
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debug("%s: init MMC\n", __func__);
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tegra_mmc_init();
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return 0;
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}
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void pad_init_mmc(struct mmc_host *host)
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{
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#if defined(CONFIG_TEGRA30)
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enum periph_id id = host->mmc_id;
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u32 val;
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debug("%s: sdmmc address = %08x, id = %d\n", __func__,
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(unsigned int)host->reg, id);
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/* Set the pad drive strength for SDMMC1 or 3 only */
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if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
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debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
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__func__);
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return;
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}
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val = readl(&host->reg->sdmemcmppadctl);
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val &= 0xFFFFFFF0;
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val |= MEMCOMP_PADCTRL_VREF;
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writel(val, &host->reg->sdmemcmppadctl);
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val = readl(&host->reg->autocalcfg);
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val &= 0xFFFF0000;
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val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
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writel(val, &host->reg->autocalcfg);
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#endif /* T30 */
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}
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#endif /* MMC */
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#ifdef CONFIG_ARM64
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/*
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* Most hardware on 64-bit Tegra is still restricted to DMA to the lower
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* 32-bits of the physical address space. Cap the maximum usable RAM area
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* at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
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* boundary that most devices can address.
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*/
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ulong board_get_usable_ram_top(ulong total_size)
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{
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if (gd->ram_top > 0x100000000)
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return 0x100000000;
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return gd->ram_top;
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}
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#endif
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