Marek Vasut d2f7ae14d3 Revert "i.MX28: Enable additional DRAM address bits" ... This reverts commit 69d26d09de. Apparently, this commit got mainline only because of out-of-tree port and causes breakage on board that is mainline. Revert. Reason: * The OOT board has 512MB of DRAM, enabling this additional address line enabled it to work fine with 512MB of RAM. * Every mainline port has max. 256MB of DRAM, therefore this revert has no impact on any mainline port * Though this caused a problem with new M28 board with 256MB of DRAM where the chips are wired differently. The patch-to-be-reverted caused the DRAM to behave like this: [128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again] Therefore to retain the current one-memory-init-rules-them-all situation, revert this patch until another board emerges and will actually be pushed mainline that needs different setup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>		2012-05-15 08:31:32 +02:00
..
clock.c	Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers	2012-03-26 23:09:24 +02:00
iomux.c	Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8	2012-03-26 23:09:24 +02:00
Makefile	M28: Cleanup memsize.o OOT build	2011-12-09 17:30:10 +01:00
mx28_init.h	i.MX28: Move SPL to arch/arm/cpu/arm926ejs/mx28	2011-12-09 17:30:10 +01:00
mx28.c	DMA: Split the APBH DMA init into block and channel init	2012-04-16 14:53:59 +02:00
spl_boot.c	M28: Cleanup memsize.o OOT build	2011-12-09 17:30:10 +01:00
spl_mem_init.c	Revert "i.MX28: Enable additional DRAM address bits"	2012-05-15 08:31:32 +02:00
spl_power_init.c	i.MX28: Make the stabilization delays shorter	2012-03-27 09:41:16 +02:00
start.S	mx28: fix SPL code to make USB booting work	2012-02-27 21:19:23 +01:00
timer.c	MX28: Fix get_timer() / get_tbclk() issue	2012-02-27 21:19:23 +01:00
u-boot-spl.lds	M28: Cleanup memsize.o OOT build	2011-12-09 17:30:10 +01:00