mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*/
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#ifndef _TEGRA186_GPIO_PRIV_H_
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#define _TEGRA186_GPIO_PRIV_H_
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/*
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* For each GPIO, there are a set of registers than affect it, all packed
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* back-to-back.
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*/
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#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
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#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
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#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4)
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#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5)
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#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6)
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#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7)
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#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04
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#define TEGRA186_GPIO_INPUT 0x08
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#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
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#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
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#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
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#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1
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#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
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/*
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* 8 GPIOs are packed into a port. Their registers appear back-to-back in the
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* port's address space.
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*/
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#define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20
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#define TEGRA186_GPIO_PER_GPIO_COUNT 8
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/*
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* Per-port registers are packed immediately following all of a port's
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* per-GPIO registers.
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*/
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#define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100
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#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4
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#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8
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/*
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* The registers for multiple ports are packed together back-to-back to form
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* the overall controller.
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*/
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#define TEGRA186_GPIO_PER_PORT_STRIDE 0x200
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#endif
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