mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 19:09:43 +09:00
d263cda5ae
The relocate_code function was handling cache maintenance incorrectly. It copied U-Boot to its new location, flushed the caches & then proceeded to apply relocations & jump to the new code without flushing the caches again. This is problematic as the instruction cache could potentially have already fetched instructions that hadn't had relocs applied. Rework this to perform the flush_cache call using the code in the original copy of U-Boot, after having applied relocations to the new copy of U-Boot. The new U-Boot can then be jumped to safely once that cache flush has been performed. As part of this, since the old U-Boot is used up until after that cache flush, complexity around loading values from the GOT using a jump & link instruction & loads from a table is removed. Instead we can simply load the needed values with PTR_LA fromt the original GOT. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
323 lines
6.5 KiB
ArmAsm
323 lines
6.5 KiB
ArmAsm
/*
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* Startup Code for MIPS32 CPU-core
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#ifndef CONFIG_SYS_INIT_SP_ADDR
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
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CONFIG_SYS_INIT_SP_OFFSET)
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#endif
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#ifdef CONFIG_32BIT
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# define MIPS_RELOC 3
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# define STATUS_SET 0
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#endif
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#ifdef CONFIG_64BIT
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# ifdef CONFIG_SYS_LITTLE_ENDIAN
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# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
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(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
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# else
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# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
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((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
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# endif
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# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
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# define STATUS_SET ST0_KX
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#endif
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/*
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* For the moment disable interrupts, mark the kernel mode and
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* set ST0_KX so that the CPU does not spit fire when using
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* 64-bit addresses.
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*/
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.macro setup_c0_status set clr
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.set push
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mfc0 t0, CP0_STATUS
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or t0, ST0_CU0 | \set | 0x1f | \clr
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xor t0, 0x1f | \clr
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mtc0 t0, CP0_STATUS
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.set noreorder
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sll zero, 3 # ehb
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.set pop
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.endm
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.set noreorder
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ENTRY(_start)
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/* U-Boot entry point */
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b reset
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nop
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.org 0x10
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#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
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/*
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* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
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* access external NOR flashes. If the board boots from NOR flash the
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* internal BootROM does a blind read at address 0xB0000010 to read the
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* initial configuration for that EBU in order to access the flash
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* device with correct parameters. This config option is board-specific.
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*/
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.word CONFIG_SYS_XWAY_EBU_BOOTCFG
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.word 0x0
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#elif defined(CONFIG_MALTA)
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/*
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* Linux expects the Board ID here.
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*/
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.word 0x00000420 # 0x420 (Malta Board with CoreLV)
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.word 0x00000000
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#endif
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.org 0x200
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/* TLB refill, 32 bit task */
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1: b 1b
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nop
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.org 0x280
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/* XTLB refill, 64 bit task */
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1: b 1b
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nop
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.org 0x300
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/* Cache error exception */
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1: b 1b
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nop
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.org 0x380
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/* General exception */
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1: b 1b
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nop
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.org 0x400
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/* Catch interrupt exceptions */
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1: b 1b
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nop
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.org 0x480
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/* EJTAG debug exception */
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1: b 1b
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nop
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.align 4
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reset:
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/* Clear watch registers */
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MTC0 zero, CP0_WATCHLO
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mtc0 zero, CP0_WATCHHI
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/* WP(Watch Pending), SW0/1 should be cleared */
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mtc0 zero, CP0_CAUSE
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setup_c0_status STATUS_SET 0
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/* Init Timer */
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mtc0 zero, CP0_COUNT
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mtc0 zero, CP0_COMPARE
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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mfc0 t0, CP0_CONFIG
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and t0, t0, MIPS_CONF_IMPL
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or t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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ehb
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#endif
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/*
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* Initialize $gp, force pointer sized alignment of bal instruction to
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* forbid the compiler to put nop's between bal and _gp. This is
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* required to keep _gp and ra aligned to 8 byte.
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*/
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.align PTRLOG
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bal 1f
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nop
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PTR _gp
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1:
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PTR_L gp, 0(ra)
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#ifdef CONFIG_MIPS_CM
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PTR_LA t9, mips_cm_map
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jalr t9
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nop
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#endif
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* Initialize any external memory */
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PTR_LA t9, lowlevel_init
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jalr t9
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nop
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# endif
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/* Initialize caches... */
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PTR_LA t9, mips_cache_reset
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jalr t9
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nop
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# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* Initialize any external memory */
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PTR_LA t9, lowlevel_init
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jalr t9
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nop
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# endif
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#endif
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/* Set up temporary stack */
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li t0, -16
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PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
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and sp, t1, t0 # force 16 byte alignment
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PTR_SUBU \
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sp, sp, GD_SIZE # reserve space for gd
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and sp, sp, t0 # force 16 byte alignment
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move k0, sp # save gd pointer
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#ifdef CONFIG_SYS_MALLOC_F_LEN
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li t2, CONFIG_SYS_MALLOC_F_LEN
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PTR_SUBU \
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sp, sp, t2 # reserve space for early malloc
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and sp, sp, t0 # force 16 byte alignment
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#endif
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move fp, sp
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/* Clear gd */
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move t0, k0
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1:
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PTR_S zero, 0(t0)
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blt t0, t1, 1b
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PTR_ADDIU t0, PTRSIZE
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#ifdef CONFIG_SYS_MALLOC_F_LEN
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PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
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#endif
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move a0, zero # a0 <-- boot_flags = 0
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PTR_LA t9, board_init_f
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jr t9
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move ra, zero
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END(_start)
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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* a0 = addr_sp
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* a1 = gd
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* a2 = destination address
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*/
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ENTRY(relocate_code)
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move sp, a0 # set new stack pointer
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move fp, sp
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move s0, a1 # save gd in s0
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move s2, a2 # save destination address in s2
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PTR_LI t0, CONFIG_SYS_MONITOR_BASE
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PTR_SUB s1, s2, t0 # s1 <-- relocation offset
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PTR_LA t2, __image_copy_end
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move t1, a2
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/*
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* t0 = source address
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* t1 = target address
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* t2 = source end address
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*/
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1:
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PTR_L t3, 0(t0)
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PTR_S t3, 0(t1)
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PTR_ADDU t0, PTRSIZE
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blt t0, t2, 1b
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PTR_ADDU t1, PTRSIZE
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/*
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* Now we want to update GOT.
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*
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* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
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* generated by GNU ld. Skip these reserved entries from relocation.
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*/
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PTR_LA t3, num_got_entries
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PTR_LA t8, _GLOBAL_OFFSET_TABLE_
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PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
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PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
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PTR_LI t2, 2
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1:
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PTR_L t1, 0(t8)
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beqz t1, 2f
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PTR_ADD t1, s1
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PTR_S t1, 0(t8)
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2:
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PTR_ADDIU t2, 1
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blt t2, t3, 1b
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PTR_ADDIU t8, PTRSIZE
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/* Update dynamic relocations */
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PTR_LA t1, __rel_dyn_start
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PTR_LA t2, __rel_dyn_end
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b 2f # skip first reserved entry
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PTR_ADDIU t1, 2 * PTRSIZE
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1:
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lw t8, -4(t1) # t8 <-- relocation info
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PTR_LI t3, MIPS_RELOC
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bne t8, t3, 2f # skip non-MIPS_RELOC entries
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nop
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PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
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PTR_L t8, 0(t3) # t8 <-- original pointer
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PTR_ADD t8, s1 # t8 <-- adjusted pointer
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PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
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PTR_S t8, 0(t3)
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2:
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blt t1, t2, 1b
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PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
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/*
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* Flush caches to ensure our newly modified instructions are visible
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* to the instruction cache. We're still running with the old GOT, so
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* apply the reloc offset to the start address.
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*/
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PTR_LA a0, __text_start
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PTR_LA a1, __text_end
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PTR_SUB a1, a1, a0
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PTR_LA t9, flush_cache
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jalr t9
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PTR_ADD a0, s1
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PTR_ADD gp, s1 # adjust gp
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/*
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* Clear BSS
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*
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* GOT is now relocated. Thus __bss_start and __bss_end can be
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* accessed directly via $gp.
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*/
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PTR_LA t1, __bss_start # t1 <-- __bss_start
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PTR_LA t2, __bss_end # t2 <-- __bss_end
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1:
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PTR_S zero, 0(t1)
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blt t1, t2, 1b
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PTR_ADDIU t1, PTRSIZE
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move a0, s0 # a0 <-- gd
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move a1, s2
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PTR_LA t9, board_init_r
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jr t9
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move ra, zero
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END(relocate_code)
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