mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-05 01:33:44 +09:00
d26154c9a6
The spd_dram code shifts the base address, then masks 20 bits, but forgets to shift the base address back. Fix this by just masking the base address correctly. Found this bug while trying to relocate a DDR memory at the base != 0. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
158 lines
3.5 KiB
C
158 lines
3.5 KiB
C
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
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*
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* (C) Copyright 2008
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <pci.h>
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#include <spi.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#include "mvblm7.h"
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CFG_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1);
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ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1)
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return -1;
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}
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im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
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LAWAR_SIZE);
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im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
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im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
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im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CFG_DDR_MODE;
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im->ddr.sdram_interval = CFG_DDR_INTERVAL;
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im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
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udelay(300);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return CFG_DDR_SIZE;
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}
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
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msize = fixed_sdram();
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/* return total bus RAM size(bytes) */
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return msize * 1024 * 1024;
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}
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int checkboard(void)
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{
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puts("Board: Matrix Vision mvBlueLYNX-M7\n");
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return 0;
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}
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u8 *dhcp_vendorex_prep(u8 *e)
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{
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char *ptr;
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/* DHCP vendor-class-identifier = 60 */
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ptr = getenv("dhcp_vendor-class-identifier");
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if (ptr) {
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*e++ = 60;
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*e++ = strlen(ptr);
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while (*ptr)
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*e++ = *ptr++;
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}
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/* DHCP_CLIENT_IDENTIFIER = 61 */
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ptr = getenv("dhcp_client_id");
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if (ptr) {
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*e++ = 61;
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*e++ = strlen(ptr);
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while (*ptr)
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*e++ = *ptr++;
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}
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return e;
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}
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u8 *dhcp_vendorex_proc(u8 *popt)
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{
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return NULL;
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}
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#ifdef CONFIG_HARD_SPI
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
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iopd->dat &= ~MVBLM7_MMC_CS;
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
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iopd->dat |= ~MVBLM7_MMC_CS;
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif
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