mirror of
https://github.com/brain-hackers/u-boot-brain
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f56348af5d
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9 Cortex A8 and A9 both belong to the armv7 architecture, hence the name change. The two architectures are similar enough that substantial code can be shared. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
310 lines
9.5 KiB
C
310 lines
9.5 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* (C) Copyright 2009
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* Frederik Kriewitz <frederik@kriewitz.eu>
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*
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* Configuration settings for the DevKit8000 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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#define CONFIG_OMAP3430 1 /* which is in a 3430 */
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#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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/* Display CPU and Board information */
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/* Size of malloc() pool */
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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/* Sector */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
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/* initial data */
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/* Hardware drivers */
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/* DDR - I use Micron DDR */
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#define CONFIG_OMAP3_MICRON_DDR 1
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/* DM9000 */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_DRIVER_DM9000 1
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#define CONFIG_DM9000_BASE 0x2c000000
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
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#define CONFIG_DM9000_USE_16BIT 1
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#define CONFIG_DM9000_NO_SROM 1
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#undef CONFIG_DM9000_DEBUG
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/* NS16550 Configuration */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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/* select serial console configuration */
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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#define CONFIG_SERIAL3 3
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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/* MMC */
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#define CONFIG_MMC 1
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#define CONFIG_OMAP3_MMC 1
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#define CONFIG_DOS_PARTITION 1
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/* I2C */
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_BUS 0
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#define CONFIG_SYS_I2C_BUS_SELECT 1
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#define CONFIG_DRIVER_OMAP34XX_I2C 1
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/* TWL4030 */
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#define CONFIG_TWL4030_POWER 1
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#define CONFIG_TWL4030_LED 1
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/* Board NAND Info */
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#define CONFIG_SYS_NO_FLASH /* no NOR flash */
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define MTDIDS_DEFAULT "nand0=nand"
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#define MTDPARTS_DEFAULT "mtdparts=nand:" \
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"512k(x-loader)," \
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"1920k(u-boot)," \
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"128k(u-boot-env)," \
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"4m(kernel)," \
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"-(fs)"
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
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/* partition */
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/* commands to include */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP /* DHCP support */
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
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#define CONFIG_CMD_NAND /* NAND support */
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#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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/* BOOTP/DHCP options */
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_NISDOMAIN
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_BOOTP_NTPSERVER
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#define CONFIG_BOOTP_TIMEOFFSET
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#undef CONFIG_BOOTP_VENDOREX
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/* Environment information */
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#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x82000000\0" \
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"console=ttyS2,115200n8\0" \
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"vram=12M\0" \
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"dvimode=1024x768MR-16@60\0" \
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"defaultdisplay=dvi\0" \
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"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
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"kernelopts=rw\0" \
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"commonargs=" \
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"setenv bootargs console=${console} " \
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay}\0" \
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"mmcargs=" \
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"run commonargs; " \
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"setenv bootargs ${bootargs} " \
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"root=/dev/mmcblk0p2 " \
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"${kernelopts}\0" \
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"nandargs=" \
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"run commonargs; " \
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"setenv bootargs ${bootargs} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=/dev/mtdblock4 " \
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"rootfstype=jffs2 " \
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"${kernelopts}\0" \
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"netargs=" \
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"run commonargs; " \
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"setenv bootargs ${bootargs} " \
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"root=/dev/nfs " \
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"nfsroot=${serverip}:${rootpath},${nfsopts} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
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"${kernelopts} " \
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"dnsip1=${dnsip} " \
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"dnsip2=${dnsip2}\0" \
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"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
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"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nand read ${loadaddr} 280000 400000; " \
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"bootm ${loadaddr}\0" \
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"netboot=echo Booting from network ...; " \
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"dhcp ${loadaddr}; " \
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"run netargs; " \
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"bootm ${loadaddr}\0" \
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"autoboot=if mmc init 0; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run nandboot; " \
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"fi; " \
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"fi; " \
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"else run nandboot; fi\0"
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#define CONFIG_BOOTCOMMAND "run autoboot"
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_AUTO_COMPLETE 1
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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0x01000000) /* 16MB */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/* The stack sizes are set up in start.S using the settings below */
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#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
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#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
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#endif
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/* SDRAM Bank Allocation method */
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#define SDRC_R_B_C 1
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/* NAND and environment organization */
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#define CONFIG_ENV_IS_IN_NAND 1
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_ENV_OFFSET boot_flash_off
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#ifndef __ASSEMBLY__
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extern unsigned int boot_flash_base;
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extern volatile unsigned int boot_flash_env_addr;
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extern unsigned int boot_flash_off;
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extern unsigned int boot_flash_sec;
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extern unsigned int boot_flash_type;
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#endif
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#endif /* __CONFIG_H */
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