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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
202 lines
4.9 KiB
C
202 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
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*/
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#include <common.h>
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#include <environment.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <phy.h>
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#include <cpsw.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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#if defined(CONFIG_SPL_BUILD)
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/* DDR3 RAM timings */
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K128MJT187E_RD_DQS,
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.datawdsratio0 = MT41K128MJT187E_WR_DQS,
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.datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K128MJT187E_RATIO,
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.cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
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.cmd1csratio = MT41K128MJT187E_RATIO,
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.cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
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.cmd2csratio = MT41K128MJT187E_RATIO,
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.cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K128MJT187E_EMIF_SDCFG,
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.ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
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.sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
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.sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
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.sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
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.zq_config = MT41K128MJT187E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
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PHY_EN_DYN_PWRDN,
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};
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const struct ctrl_ioregs ddr3_ioregs = {
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.cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
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.cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
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.cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE,
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.dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
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.dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return serial_tstc() && serial_getc() == 'c';
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}
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#endif
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr_266 = {
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266, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_303 = {
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303, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_400 = {
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400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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/*
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* The pengwyn board uses the TPS650250 PMIC without I2C
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* interface and will output the following fixed voltages:
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* DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
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* VLDO1=1V8 (IO) VLDO2=1V8(IO)
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* Vcore=1V1 is fixed, generated by TPS62231
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*/
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/* Get the frequency */
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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/* Set CORE Frequencies to OPP100 */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* 720MHz cpu, this might change on newer board revisions */
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dpll_mpu_opp100.m = MPUPLL_M_720;
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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/* future configs can return other clock settings */
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return &dpll_ddr_303;
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}
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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void sdram_init(void)
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{
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config_ddr(303, &ddr3_ioregs, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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}
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#endif /* if CONFIG_SPL_BUILD */
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gpmc_init();
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return 0;
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}
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#ifdef CONFIG_DRIVER_TI_CPSW
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 1,
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.phy_if = PHY_INTERFACE_MODE_MII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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int board_eth_init(bd_t *bis)
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{
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int rv, n = 0;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
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printf("<ethaddr> not set. Reading from E-fuse\n");
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("ethaddr", mac_addr);
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else
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return n;
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}
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writel(MII_MODE_ENABLE, &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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return n;
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}
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#endif /* if CONFIG_DRIVER_TI_CPSW */
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