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https://github.com/brain-hackers/u-boot-brain
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![Thomas Weber](/assets/img/avatar_default.png)
Use the return value of cmd_usage instead of ignoring this and returning a 1. Signed-off-by: Thomas Weber <weber@corscience.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
246 lines
5.7 KiB
C
246 lines
5.7 KiB
C
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include "fpga.h"
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#define CH7301_I2C_ADDR 0x75
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#define PIXCLK_640_480_60 25180000
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#define BASE_WIDTH 32
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#define BASE_HEIGHT 16
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#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
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enum {
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REG_CONTROL = 0x0010,
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REG_MPC3W_CONTROL = 0x001a,
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REG_VIDEOCONTROL = 0x0042,
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REG_OSDVERSION = 0x0100,
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REG_OSDFEATURES = 0x0102,
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REG_OSDCONTROL = 0x0104,
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REG_XY_SIZE = 0x0106,
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REG_VIDEOMEM = 0x0800,
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};
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enum {
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CH7301_CM = 0x1c, /* Clock Mode Register */
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CH7301_IC = 0x1d, /* Input Clock Register */
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CH7301_GPIO = 0x1e, /* GPIO Control Register */
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CH7301_IDF = 0x1f, /* Input Data Format Register */
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CH7301_CD = 0x20, /* Connection Detect Register */
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CH7301_DC = 0x21, /* DAC Control Register */
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CH7301_HPD = 0x23, /* Hot Plug Detection Register */
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CH7301_TCTL = 0x31, /* DVI Control Input Register */
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CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
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CH7301_TPD = 0x34, /* DVI PLL Divide Register */
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CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
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CH7301_TPF = 0x36, /* DVI PLL Filter Register */
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CH7301_TCT = 0x37, /* DVI Clock Test Register */
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CH7301_TSTP = 0x48, /* Test Pattern Register */
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CH7301_PM = 0x49, /* Power Management register */
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CH7301_VID = 0x4a, /* Version ID Register */
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CH7301_DID = 0x4b, /* Device ID Register */
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CH7301_DSP = 0x56, /* DVI Sync polarity Register */
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};
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static void mpc92469ac_calc_parameters(unsigned int fout,
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unsigned int *post_div, unsigned int *feedback_div)
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{
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unsigned int n = *post_div;
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unsigned int m = *feedback_div;
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unsigned int a;
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unsigned int b = 14745600 / 16;
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if (fout < 50169600)
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n = 8;
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else if (fout < 100339199)
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n = 4;
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else if (fout < 200678399)
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n = 2;
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else
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n = 1;
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a = fout * n + (b / 2); /* add b/2 for proper rounding */
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m = a / b;
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*post_div = n;
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*feedback_div = m;
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}
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static void mpc92469ac_set(unsigned int fout)
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{
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unsigned int n;
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unsigned int m;
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unsigned int bitval = 0;
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mpc92469ac_calc_parameters(fout, &n, &m);
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switch (n) {
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case 1:
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bitval = 0x00;
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break;
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case 2:
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bitval = 0x01;
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break;
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case 4:
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bitval = 0x02;
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break;
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case 8:
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bitval = 0x03;
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break;
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}
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fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
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}
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static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
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{
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unsigned int k;
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for (k = 0; k < charcount; ++k) {
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if (offset + k >= BUFSIZE)
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return -1;
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fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
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}
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return charcount;
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}
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static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned x;
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unsigned y;
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unsigned charcount;
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unsigned len;
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u8 color;
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unsigned int k;
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u16 buf[BUFSIZE];
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char *text;
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if (argc < 5) {
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return cmd_usage(cmdtp);
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}
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x = simple_strtoul(argv[1], NULL, 16);
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y = simple_strtoul(argv[2], NULL, 16);
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color = simple_strtoul(argv[3], NULL, 16);
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text = argv[4];
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charcount = strlen(text);
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len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
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for (k = 0; k < len; ++k)
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buf[k] = (text[k] << 8) | color;
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return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
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}
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int osd_probe(void)
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{
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u8 value;
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u16 version = fpga_get_reg(REG_OSDVERSION);
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u16 features = fpga_get_reg(REG_OSDFEATURES);
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unsigned width;
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unsigned height;
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width = ((features & 0x3f00) >> 8) + 1;
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height = (features & 0x001f) + 1;
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printf("OSD: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
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version/100, version%100, width, height);
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value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
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if (value != 0x17) {
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printf(" Probing CH7301 failed, DID %02x\n", value);
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return -1;
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}
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
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mpc92469ac_set(PIXCLK_640_480_60);
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fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
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fpga_set_reg(REG_OSDCONTROL, 0x0049);
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fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
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return 0;
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}
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int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned x;
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unsigned y;
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unsigned k;
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u16 buffer[BASE_WIDTH];
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char *rp;
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u16 *wp = buffer;
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unsigned count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
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if ((argc < 4) || (strlen(argv[3]) % 4)) {
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return cmd_usage(cmdtp);
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}
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x = simple_strtoul(argv[1], NULL, 16);
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y = simple_strtoul(argv[2], NULL, 16);
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rp = argv[3];
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while (*rp) {
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char substr[5];
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memcpy(substr, rp, 4);
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substr[4] = 0;
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*wp = simple_strtoul(substr, NULL, 16);
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rp += 4;
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wp++;
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if (wp - buffer > BASE_WIDTH)
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break;
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}
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for (k = 0; k < count; ++k) {
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unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
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osd_write_videomem(offset, buffer, wp - buffer);
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}
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return 0;
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}
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U_BOOT_CMD(
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osdw, 5, 0, osd_write,
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"write 16-bit hex encoded buffer to osd memory",
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"pos_x pos_y buffer count\n"
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);
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U_BOOT_CMD(
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osdp, 5, 0, osd_print,
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"write ASCII buffer to osd memory",
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"pos_x pos_y color text\n"
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);
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