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https://github.com/brain-hackers/u-boot-brain
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3bd8437dcc
It's possible to need to call this function on the same banks multiple times so we want to be sure that 'pos A' is cleared out again at the end. Signed-off-by: Tom Rini <trini@ti.com>
167 lines
4.4 KiB
C
167 lines
4.4 KiB
C
/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Manikandan Pillai <mani.pillai@ti.com>
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*
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* Initial Code from:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <command.h>
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struct gpmc *gpmc_cfg;
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#if defined(CONFIG_CMD_NAND)
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static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
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M_NAND_GPMC_CONFIG1,
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M_NAND_GPMC_CONFIG2,
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M_NAND_GPMC_CONFIG3,
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M_NAND_GPMC_CONFIG4,
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M_NAND_GPMC_CONFIG5,
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M_NAND_GPMC_CONFIG6, 0
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};
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#if defined(CONFIG_ENV_IS_IN_NAND)
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#define GPMC_CS 0
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#else
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#define GPMC_CS 1
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#endif
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#endif
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#if defined(CONFIG_CMD_ONENAND)
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static const u32 gpmc_onenand[GPMC_MAX_REG] = {
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ONENAND_GPMC_CONFIG1,
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ONENAND_GPMC_CONFIG2,
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ONENAND_GPMC_CONFIG3,
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ONENAND_GPMC_CONFIG4,
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ONENAND_GPMC_CONFIG5,
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ONENAND_GPMC_CONFIG6, 0
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};
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#if defined(CONFIG_ENV_IS_IN_ONENAND)
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#define GPMC_CS 0
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#else
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#define GPMC_CS 1
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#endif
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#endif
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in guessing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(u32 cs)
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{
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u32 val1, val2, addr;
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u32 pattern = 0x12345678;
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addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
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writel(0x0, addr + 0x400); /* clear pos A */
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writel(pattern, addr); /* pattern to pos B */
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writel(0x0, addr + 4); /* remove pattern off the bus */
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val1 = readl(addr + 0x400); /* get pos A value */
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val2 = readl(addr); /* get val2 */
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writel(0x0, addr + 0x400); /* clear pos A */
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if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
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return 0;
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else
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return 1;
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}
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
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u32 size)
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{
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writel(0, &cs->config7);
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sdelay(1000);
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/* Delay for settling */
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writel(gpmc_config[0], &cs->config1);
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writel(gpmc_config[1], &cs->config2);
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writel(gpmc_config[2], &cs->config3);
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writel(gpmc_config[3], &cs->config4);
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writel(gpmc_config[4], &cs->config5);
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writel(gpmc_config[5], &cs->config6);
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/*
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* Enable the config. size is the CS size and goes in
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* bits 11:8. We set bit 6 to enable this CS and the base
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* address goes into bits 5:0.
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*/
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writel((size << 8) | (GPMC_CS_ENABLE << 6) |
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((base >> 24) & GPMC_BASEADDR_MASK),
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&cs->config7);
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sdelay(2000);
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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/* putting a blanket check on GPMC based on ZeBu for now */
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gpmc_cfg = (struct gpmc *)GPMC_BASE;
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#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
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const u32 *gpmc_config = NULL;
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u32 base = 0;
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u32 size = 0;
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#endif
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u32 config = 0;
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/* global settings */
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writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
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writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
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config = readl(&gpmc_cfg->config);
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config &= (~0xf00);
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writel(config, &gpmc_cfg->config);
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/*
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* Disable the GPMC0 config set by ROM code
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* It conflicts with our MPDB (both at 0x08000000)
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*/
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writel(0, &gpmc_cfg->cs[0].config7);
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sdelay(1000);
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#if defined(CONFIG_CMD_NAND) /* CS 0 */
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gpmc_config = gpmc_m_nand;
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base = PISMO1_NAND_BASE;
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size = PISMO1_NAND_SIZE;
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enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
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#endif
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#if defined(CONFIG_CMD_ONENAND)
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gpmc_config = gpmc_onenand;
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base = PISMO1_ONEN_BASE;
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size = PISMO1_ONEN_SIZE;
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enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
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#endif
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}
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