mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
700a0c648d
Old, obsolete and duplicated code was cleaned up and replace by the new partitioning method. There are two possible approaches now: * define a single, static partition * use mtdparts command line option and dynamic partitioning Default is static partitioning.
493 lines
12 KiB
C
493 lines
12 KiB
C
/*
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* (C) Copyright 2000, 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
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* Add support the Sharp chips on the mpc8260ads.
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* I started with board/ip860/flash.c and made changes I found in
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* the MTD project by David Schleef.
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*
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* (C) Copyright 2003 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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* Re-written to support multi-bank flash SIMMs.
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* Added support for real protection and JFFS2.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/* Intel-compatible flash ID */
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#define INTEL_COMPAT 0x89898989
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#define INTEL_ALT 0xB0B0B0B0
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/* Intel-compatible flash commands */
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#define INTEL_PROGRAM 0x10101010
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#define INTEL_ERASE 0x20202020
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#define INTEL_CLEAR 0x50505050
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#define INTEL_LOCKBIT 0x60606060
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#define INTEL_PROTECT 0x01010101
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#define INTEL_STATUS 0x70707070
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#define INTEL_READID 0x90909090
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#define INTEL_CONFIRM 0xD0D0D0D0
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#define INTEL_RESET 0xFFFFFFFF
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/* Intel-compatible flash status bits */
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#define INTEL_FINISHED 0x80808080
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#define INTEL_OK 0x80808080
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*-----------------------------------------------------------------------
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* This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
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* Up to 32MB of flash supported (up to 4 banks.)
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* BCSR is used for flash presence detect (page 4-65 of the User's Manual)
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*
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* The following code can not run from flash!
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*/
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unsigned long flash_init (void)
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{
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ulong size = 0, sect_start, sect_size = 0, bank_size;
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ushort sect_count = 0;
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int i, j, nbanks;
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vu_long *addr = (vu_long *)CFG_FLASH_BASE;
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vu_long *bcsr = (vu_long *)CFG_BCSR;
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switch (bcsr[2] & 0xF) {
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case 0:
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nbanks = 4;
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break;
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case 1:
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nbanks = 2;
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break;
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case 2:
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nbanks = 1;
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break;
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default: /* Unsupported configurations */
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nbanks = CFG_MAX_FLASH_BANKS;
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}
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if (nbanks > CFG_MAX_FLASH_BANKS)
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nbanks = CFG_MAX_FLASH_BANKS;
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for (i = 0; i < nbanks; i++) {
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*addr = INTEL_READID; /* Read Intelligent Identifier */
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if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
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switch (addr[1]) {
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case SHARP_ID_28F016SCL:
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case SHARP_ID_28F016SCZ:
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flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
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sect_count = 32;
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sect_size = 0x40000;
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break;
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default:
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flash_info[i].flash_id = FLASH_UNKNOWN;
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sect_count = CFG_MAX_FLASH_SECT;
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sect_size =
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CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
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}
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}
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else
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flash_info[i].flash_id = FLASH_UNKNOWN;
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if (flash_info[i].flash_id == FLASH_UNKNOWN) {
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printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
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addr[0], addr[1], (ulong)addr);
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size = 0;
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*addr = INTEL_RESET; /* Reset bank to Read Array mode */
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break;
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}
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flash_info[i].sector_count = sect_count;
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flash_info[i].size = bank_size = sect_size * sect_count;
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size += bank_size;
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sect_start = (ulong)addr;
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for (j = 0; j < sect_count; j++) {
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addr = (vu_long *)sect_start;
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flash_info[i].start[j] = sect_start;
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flash_info[i].protect[j] = (addr[2] == 0x01010101);
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sect_start += sect_size;
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}
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*addr = INTEL_RESET; /* Reset bank to Read Array mode */
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addr = (vu_long *)sect_start;
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}
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if (size == 0) { /* Unknown flash, fill with hard-coded values */
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sect_start = CFG_FLASH_BASE;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
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flash_info[i].sector_count = sect_count;
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for (j = 0; j < sect_count; j++) {
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flash_info[i].start[j] = sect_start;
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flash_info[i].protect[j] = 0;
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sect_start += sect_size;
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}
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}
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size = CFG_FLASH_SIZE;
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}
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else
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for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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flash_info[i].size = 0;
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flash_info[i].sector_count = 0;
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}
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE+monitor_flash_len-1,
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&flash_info[0]);
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#endif
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#ifdef CFG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
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&flash_info[0]);
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#endif
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return (size);
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_INTEL: printf ("Intel "); break;
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case FLASH_MAN_SHARP: printf ("Sharp "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
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break;
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case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
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break;
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case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
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break;
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case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " "
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);
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}
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printf ("\n");
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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int flag, prot, sect;
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ulong start, now, last;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
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&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
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printf ("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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prot = 0;
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for (sect=s_first; sect<=s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect<=s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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vu_long *addr = (vu_long *)(info->start[sect]);
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last = start = get_timer (0);
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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/* Clear Status Register */
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*addr = INTEL_CLEAR;
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/* Single Block Erase Command */
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*addr = INTEL_ERASE;
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/* Confirm */
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*addr = INTEL_CONFIRM;
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if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
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/* Resume Command, as per errata update */
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*addr = INTEL_CONFIRM;
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}
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
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if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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*addr = INTEL_RESET; /* reset bank */
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return 1;
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}
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/* show that we're waiting */
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if ((now - last) > 1000) { /* every second */
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putc ('.');
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last = now;
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}
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}
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if (*addr != INTEL_OK) {
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printf("Block erase failed at %08X, CSR=%08X\n",
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(uint)addr, (uint)*addr);
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*addr = INTEL_RESET; /* reset bank */
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return 1;
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}
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/* reset to read mode */
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*addr = INTEL_RESET;
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}
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}
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printf (" done\n");
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return 0;
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}
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/*-----------------------------------------------------------------------
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* Write a word to Flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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static int write_word (flash_info_t *info, ulong dest, ulong data)
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{
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ulong start;
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int rc = 0;
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int flag;
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vu_long *addr = (vu_long *)dest;
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/* Check if Flash is (sufficiently) erased */
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if ((*addr & data) != data) {
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return (2);
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}
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*addr = INTEL_CLEAR; /* Clear status register */
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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/* Write Command */
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*addr = INTEL_PROGRAM;
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/* Write Data */
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*addr = data;
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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/* data polling for D7 */
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start = get_timer (0);
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while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
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if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
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printf("Write timed out\n");
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rc = 1;
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break;
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}
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}
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if (*addr != INTEL_OK) {
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printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
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rc = 1;
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}
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*addr = INTEL_RESET; /* Reset to read array mode */
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return rc;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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ulong cp, wp, data;
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int i, l, rc;
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wp = (addr & ~3); /* get lower word aligned address */
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*(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - wp) != 0) {
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data = 0;
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for (i=0, cp=wp; i<l; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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for (; i<4 && cnt>0; ++i) {
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data = (data << 8) | *src++;
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--cnt;
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++cp;
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}
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for (; cnt==0 && i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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wp += 4;
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}
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/*
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* handle word aligned part
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*/
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while (cnt >= 4) {
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data = 0;
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for (i=0; i<4; ++i) {
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data = (data << 8) | *src++;
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}
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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wp += 4;
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cnt -= 4;
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}
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if (cnt == 0) {
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return (0);
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}
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/*
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* handle unaligned tail bytes
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*/
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data = 0;
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for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
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data = (data << 8) | *src++;
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--cnt;
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}
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for (; i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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rc = write_word(info, wp, data);
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return rc;
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}
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/*-----------------------------------------------------------------------
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* Set/Clear sector's lock bit, returns:
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* 0 - OK
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* 1 - Error (timeout, voltage problems, etc.)
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*/
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int flash_real_protect(flash_info_t *info, long sector, int prot)
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{
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ulong start;
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int i;
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int rc = 0;
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vu_long *addr = (vu_long *)(info->start[sector]);
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int flag = disable_interrupts();
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*addr = INTEL_CLEAR; /* Clear status register */
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if (prot) { /* Set sector lock bit */
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*addr = INTEL_LOCKBIT; /* Sector lock bit */
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*addr = INTEL_PROTECT; /* set */
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}
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else { /* Clear sector lock bit */
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*addr = INTEL_LOCKBIT; /* All sectors lock bits */
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*addr = INTEL_CONFIRM; /* clear */
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}
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start = get_timer(0);
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while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
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if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
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printf("Flash lock bit operation timed out\n");
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rc = 1;
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break;
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}
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}
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if (*addr != INTEL_OK) {
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printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
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(uint)addr, (uint)*addr);
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rc = 1;
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}
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if (!rc)
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info->protect[sector] = prot;
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/*
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* Clear lock bit command clears all sectors lock bits, so
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* we have to restore lock bits of protected sectors.
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*/
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if (!prot)
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for (i = 0; i < info->sector_count; i++)
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if (info->protect[i]) {
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addr = (vu_long *)(info->start[i]);
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*addr = INTEL_LOCKBIT; /* Sector lock bit */
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*addr = INTEL_PROTECT; /* set */
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udelay(CFG_FLASH_LOCK_TOUT * 1000);
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}
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if (flag)
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enable_interrupts();
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*addr = INTEL_RESET; /* Reset to read array mode */
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return rc;
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}
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