mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-25 11:28:51 +09:00
![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
640 lines
15 KiB
C
640 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <fdtdec.h>
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#include <linux/bitops.h>
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#include <linux/libfdt.h>
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#include "pinctrl-rockchip.h"
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#define MAX_ROCKCHIP_PINS_ENTRIES 30
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#define MAX_ROCKCHIP_GPIO_PER_BANK 32
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#define RK_FUNC_GPIO 0
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static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
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{
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struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
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struct rockchip_pin_ctrl *ctrl = priv->ctrl;
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if (bank >= ctrl->nr_banks) {
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debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
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return -EINVAL;
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}
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if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
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debug("pin conf pin %d >= %d\n", pin,
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MAX_ROCKCHIP_GPIO_PER_BANK);
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return -EINVAL;
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}
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return 0;
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}
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void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
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int *reg, u8 *bit, int *mask)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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struct rockchip_pin_ctrl *ctrl = priv->ctrl;
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struct rockchip_mux_recalced_data *data;
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int i;
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for (i = 0; i < ctrl->niomux_recalced; i++) {
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data = &ctrl->iomux_recalced[i];
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if (data->num == bank->bank_num &&
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data->pin == pin)
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break;
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}
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if (i >= ctrl->niomux_recalced)
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return;
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*reg = data->reg;
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*mask = data->mask;
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*bit = data->bit;
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}
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bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
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int mux, u32 *reg, u32 *value)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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struct rockchip_pin_ctrl *ctrl = priv->ctrl;
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struct rockchip_mux_route_data *data;
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int i;
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for (i = 0; i < ctrl->niomux_routes; i++) {
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data = &ctrl->iomux_routes[i];
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if (data->bank_num == bank->bank_num &&
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data->pin == pin && data->func == mux)
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break;
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}
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if (i >= ctrl->niomux_routes)
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return false;
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*reg = data->route_offset;
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*value = data->route_val;
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return true;
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}
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int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
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{
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int offset = 0;
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if (mux_type & IOMUX_WIDTH_4BIT) {
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if ((pin % 8) >= 4)
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offset = 0x4;
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*bit = (pin % 4) * 4;
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*mask = 0xf;
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} else if (mux_type & IOMUX_WIDTH_3BIT) {
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/*
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* pin0 ~ pin4 are at first register, and
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* pin5 ~ pin7 are at second register.
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*/
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if ((pin % 8) >= 5)
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offset = 0x4;
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*bit = (pin % 8 % 5) * 3;
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*mask = 0x7;
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} else {
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*bit = (pin % 8) * 2;
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*mask = 0x3;
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}
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return offset;
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}
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static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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unsigned int val;
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int reg, ret, mask, mux_type;
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u8 bit;
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if (iomux_num > 3)
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return -EINVAL;
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if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
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debug("pin %d is unrouted\n", pin);
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return -EINVAL;
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}
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if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
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return RK_FUNC_GPIO;
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regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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? priv->regmap_pmu : priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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ret = regmap_read(regmap, reg, &val);
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if (ret)
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return ret;
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return ((val >> bit) & mask);
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}
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static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
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int index)
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{ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
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struct rockchip_pin_ctrl *ctrl = priv->ctrl;
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return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
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}
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static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
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int pin, int mux)
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{
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int iomux_num = (pin / 8);
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if (iomux_num > 3)
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return -EINVAL;
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if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
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debug("pin %d is unrouted\n", pin);
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return -EINVAL;
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}
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if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
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if (mux != IOMUX_GPIO_ONLY) {
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debug("pin %d only supports a gpio mux\n", pin);
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return -ENOTSUPP;
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}
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}
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return 0;
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}
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/*
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* Set a new mux function for a pin.
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*
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* The register is divided into the upper and lower 16 bit. When changing
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* a value, the previous register value is not read and changed. Instead
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* it seems the changed bits are marked in the upper 16 bit, while the
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* changed value gets set in the same offset in the lower 16 bit.
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* All pin settings seem to be 2 bit wide in both the upper and lower
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* parts.
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* @bank: pin bank to change
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* @pin: pin to change
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* @mux: new mux function to set
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*/
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static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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struct rockchip_pin_ctrl *ctrl = priv->ctrl;
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int iomux_num = (pin / 8);
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int ret;
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ret = rockchip_verify_mux(bank, pin, mux);
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if (ret < 0)
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return ret;
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if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
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return 0;
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debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
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if (!ctrl->set_mux)
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return -ENOTSUPP;
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ret = ctrl->set_mux(bank, pin, mux);
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return ret;
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}
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static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
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{ 2, 4, 8, 12, -1, -1, -1, -1 },
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{ 3, 6, 9, 12, -1, -1, -1, -1 },
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{ 5, 10, 15, 20, -1, -1, -1, -1 },
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{ 4, 6, 8, 10, 12, 14, 16, 18 },
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{ 4, 7, 10, 13, 16, 19, 22, 26 }
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};
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int rockchip_translate_drive_value(int type, int strength)
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{
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int i, ret;
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ret = -EINVAL;
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for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
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if (rockchip_perpin_drv_list[type][i] == strength) {
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ret = i;
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break;
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} else if (rockchip_perpin_drv_list[type][i] < 0) {
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ret = rockchip_perpin_drv_list[type][i];
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break;
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}
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}
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return ret;
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}
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static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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struct rockchip_pin_ctrl *ctrl = priv->ctrl;
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debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
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pin_num, strength);
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if (!ctrl->set_drive)
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return -ENOTSUPP;
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return ctrl->set_drive(bank, pin_num, strength);
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}
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static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
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{
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PIN_CONFIG_BIAS_DISABLE,
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PIN_CONFIG_BIAS_PULL_UP,
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PIN_CONFIG_BIAS_PULL_DOWN,
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PIN_CONFIG_BIAS_BUS_HOLD
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},
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{
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PIN_CONFIG_BIAS_DISABLE,
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PIN_CONFIG_BIAS_PULL_DOWN,
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PIN_CONFIG_BIAS_DISABLE,
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PIN_CONFIG_BIAS_PULL_UP
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},
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};
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int rockchip_translate_pull_value(int type, int pull)
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{
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int i, ret;
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ret = -EINVAL;
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for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
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i++) {
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if (rockchip_pull_list[type][i] == pull) {
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ret = i;
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break;
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}
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}
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return ret;
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}
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static int rockchip_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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struct rockchip_pin_ctrl *ctrl = priv->ctrl;
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debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
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pin_num, pull);
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if (!ctrl->set_pull)
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return -ENOTSUPP;
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return ctrl->set_pull(bank, pin_num, pull);
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}
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static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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struct rockchip_pin_ctrl *ctrl = priv->ctrl;
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debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
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pin_num, enable);
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if (!ctrl->set_schmitt)
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return -ENOTSUPP;
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return ctrl->set_schmitt(bank, pin_num, enable);
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}
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/* set the pin config settings for a specified pin */
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static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
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u32 pin, u32 param, u32 arg)
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{
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int rc;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
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case PIN_CONFIG_BIAS_BUS_HOLD:
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rc = rockchip_set_pull(bank, pin, param);
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if (rc)
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return rc;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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rc = rockchip_set_drive_perpin(bank, pin, arg);
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if (rc < 0)
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return rc;
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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rc = rockchip_set_schmitt(bank, pin, arg);
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if (rc < 0)
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return rc;
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break;
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default:
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break;
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}
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return 0;
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}
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static const struct pinconf_param rockchip_conf_params[] = {
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{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
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{ "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
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{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
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{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
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{ "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
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{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
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{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
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{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
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};
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static int rockchip_pinconf_prop_name_to_param(const char *property,
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u32 *default_value)
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{
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const struct pinconf_param *p, *end;
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p = rockchip_conf_params;
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end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
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/* See if this pctldev supports this parameter */
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for (; p < end; p++) {
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if (!strcmp(property, p->property)) {
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*default_value = p->default_value;
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return p->param;
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}
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}
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*default_value = 0;
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return -EPERM;
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}
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static int rockchip_pinctrl_set_state(struct udevice *dev,
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struct udevice *config)
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{
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struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
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struct rockchip_pin_ctrl *ctrl = priv->ctrl;
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u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
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u32 bank, pin, mux, conf, arg, default_val;
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int ret, count, i;
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const char *prop_name;
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const void *value;
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int prop_len, param;
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const u32 *data;
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ofnode node;
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#ifdef CONFIG_OF_LIVE
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const struct device_node *np;
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struct property *pp;
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#else
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int property_offset, pcfg_node;
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const void *blob = gd->fdt_blob;
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#endif
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data = dev_read_prop(config, "rockchip,pins", &count);
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if (count < 0) {
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debug("%s: bad array size %d\n", __func__, count);
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return -EINVAL;
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}
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count /= sizeof(u32);
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if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
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debug("%s: unsupported pins array count %d\n",
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__func__, count);
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return -EINVAL;
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}
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for (i = 0; i < count; i++)
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cells[i] = fdt32_to_cpu(data[i]);
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for (i = 0; i < (count >> 2); i++) {
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bank = cells[4 * i + 0];
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pin = cells[4 * i + 1];
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mux = cells[4 * i + 2];
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conf = cells[4 * i + 3];
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ret = rockchip_verify_config(dev, bank, pin);
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if (ret)
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return ret;
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ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
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if (ret)
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return ret;
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node = ofnode_get_by_phandle(conf);
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if (!ofnode_valid(node))
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return -ENODEV;
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#ifdef CONFIG_OF_LIVE
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np = ofnode_to_np(node);
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for (pp = np->properties; pp; pp = pp->next) {
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prop_name = pp->name;
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prop_len = pp->length;
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value = pp->value;
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#else
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pcfg_node = ofnode_to_offset(node);
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fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
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value = fdt_getprop_by_offset(blob, property_offset,
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&prop_name, &prop_len);
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if (!value)
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return -ENOENT;
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#endif
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param = rockchip_pinconf_prop_name_to_param(prop_name,
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&default_val);
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if (param < 0)
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break;
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if (prop_len >= sizeof(fdt32_t))
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arg = fdt32_to_cpu(*(fdt32_t *)value);
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else
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arg = default_val;
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ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
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param, arg);
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if (ret) {
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debug("%s: rockchip_pinconf_set fail: %d\n",
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__func__, ret);
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return ret;
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}
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}
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}
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return 0;
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}
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const struct pinctrl_ops rockchip_pinctrl_ops = {
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.set_state = rockchip_pinctrl_set_state,
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.get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
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};
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/* retrieve the soc specific data */
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static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
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{
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struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
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struct rockchip_pin_ctrl *ctrl =
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(struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
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struct rockchip_pin_bank *bank;
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int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
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grf_offs = ctrl->grf_mux_offset;
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pmu_offs = ctrl->pmu_mux_offset;
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drv_pmu_offs = ctrl->pmu_drv_offset;
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drv_grf_offs = ctrl->grf_drv_offset;
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bank = ctrl->pin_banks;
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for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
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int bank_pins = 0;
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bank->priv = priv;
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bank->pin_base = ctrl->nr_pins;
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ctrl->nr_pins += bank->nr_pins;
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/* calculate iomux and drv offsets */
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for (j = 0; j < 4; j++) {
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struct rockchip_iomux *iom = &bank->iomux[j];
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struct rockchip_drv *drv = &bank->drv[j];
|
|
int inc;
|
|
|
|
if (bank_pins >= bank->nr_pins)
|
|
break;
|
|
|
|
/* preset iomux offset value, set new start value */
|
|
if (iom->offset >= 0) {
|
|
if (iom->type & IOMUX_SOURCE_PMU)
|
|
pmu_offs = iom->offset;
|
|
else
|
|
grf_offs = iom->offset;
|
|
} else { /* set current iomux offset */
|
|
iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
|
|
pmu_offs : grf_offs;
|
|
}
|
|
|
|
/* preset drv offset value, set new start value */
|
|
if (drv->offset >= 0) {
|
|
if (iom->type & IOMUX_SOURCE_PMU)
|
|
drv_pmu_offs = drv->offset;
|
|
else
|
|
drv_grf_offs = drv->offset;
|
|
} else { /* set current drv offset */
|
|
drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
|
|
drv_pmu_offs : drv_grf_offs;
|
|
}
|
|
|
|
debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
|
|
i, j, iom->offset, drv->offset);
|
|
|
|
/*
|
|
* Increase offset according to iomux width.
|
|
* 4bit iomux'es are spread over two registers.
|
|
*/
|
|
inc = (iom->type & (IOMUX_WIDTH_4BIT |
|
|
IOMUX_WIDTH_3BIT |
|
|
IOMUX_8WIDTH_2BIT)) ? 8 : 4;
|
|
if (iom->type & IOMUX_SOURCE_PMU)
|
|
pmu_offs += inc;
|
|
else
|
|
grf_offs += inc;
|
|
|
|
/*
|
|
* Increase offset according to drv width.
|
|
* 3bit drive-strenth'es are spread over two registers.
|
|
*/
|
|
if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
|
|
(drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
|
|
inc = 8;
|
|
else
|
|
inc = 4;
|
|
|
|
if (iom->type & IOMUX_SOURCE_PMU)
|
|
drv_pmu_offs += inc;
|
|
else
|
|
drv_grf_offs += inc;
|
|
|
|
bank_pins += 8;
|
|
}
|
|
|
|
/* calculate the per-bank recalced_mask */
|
|
for (j = 0; j < ctrl->niomux_recalced; j++) {
|
|
int pin = 0;
|
|
|
|
if (ctrl->iomux_recalced[j].num == bank->bank_num) {
|
|
pin = ctrl->iomux_recalced[j].pin;
|
|
bank->recalced_mask |= BIT(pin);
|
|
}
|
|
}
|
|
|
|
/* calculate the per-bank route_mask */
|
|
for (j = 0; j < ctrl->niomux_routes; j++) {
|
|
int pin = 0;
|
|
|
|
if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
|
|
pin = ctrl->iomux_routes[j].pin;
|
|
bank->route_mask |= BIT(pin);
|
|
}
|
|
}
|
|
}
|
|
|
|
return ctrl;
|
|
}
|
|
|
|
int rockchip_pinctrl_probe(struct udevice *dev)
|
|
{
|
|
struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
|
|
struct rockchip_pin_ctrl *ctrl;
|
|
struct udevice *syscon;
|
|
struct regmap *regmap;
|
|
int ret = 0;
|
|
|
|
/* get rockchip grf syscon phandle */
|
|
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
|
|
&syscon);
|
|
if (ret) {
|
|
debug("unable to find rockchip,grf syscon device (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/* get grf-reg base address */
|
|
regmap = syscon_get_regmap(syscon);
|
|
if (!regmap) {
|
|
debug("unable to find rockchip grf regmap\n");
|
|
return -ENODEV;
|
|
}
|
|
priv->regmap_base = regmap;
|
|
|
|
/* option: get pmu-reg base address */
|
|
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
|
|
&syscon);
|
|
if (!ret) {
|
|
/* get pmugrf-reg base address */
|
|
regmap = syscon_get_regmap(syscon);
|
|
if (!regmap) {
|
|
debug("unable to find rockchip pmu regmap\n");
|
|
return -ENODEV;
|
|
}
|
|
priv->regmap_pmu = regmap;
|
|
}
|
|
|
|
ctrl = rockchip_pinctrl_get_soc_data(dev);
|
|
if (!ctrl) {
|
|
debug("driver data not available\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->ctrl = ctrl;
|
|
return 0;
|
|
}
|