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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
170 lines
3.9 KiB
C
170 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <command.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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#include <asm/mmu.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <linux/libfdt.h>
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#endif
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#if defined(CONFIG_PQ_MDS_PIB)
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#include "../common/pq-mds-pib.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* ETH3 */
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{1, 0, 1, 0, 1}, /* TxD0 */
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{1, 1, 1, 0, 1}, /* TxD1 */
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{1, 2, 1, 0, 1}, /* TxD2 */
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{1, 3, 1, 0, 1}, /* TxD3 */
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{1, 9, 1, 0, 1}, /* TxER */
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{1, 12, 1, 0, 1}, /* TxEN */
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{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
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{1, 4, 2, 0, 1}, /* RxD0 */
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{1, 5, 2, 0, 1}, /* RxD1 */
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{1, 6, 2, 0, 1}, /* RxD2 */
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{1, 7, 2, 0, 1}, /* RxD3 */
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{1, 8, 2, 0, 1}, /* RxER */
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{1, 10, 2, 0, 1}, /* RxDV */
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{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
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{1, 11, 2, 0, 1}, /* COL */
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{1, 13, 2, 0, 1}, /* CRS */
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/* ETH4 */
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{1, 18, 1, 0, 1}, /* TxD0 */
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{1, 19, 1, 0, 1}, /* TxD1 */
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{1, 20, 1, 0, 1}, /* TxD2 */
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{1, 21, 1, 0, 1}, /* TxD3 */
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{1, 27, 1, 0, 1}, /* TxER */
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{1, 30, 1, 0, 1}, /* TxEN */
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{3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
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{1, 22, 2, 0, 1}, /* RxD0 */
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{1, 23, 2, 0, 1}, /* RxD1 */
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{1, 24, 2, 0, 1}, /* RxD2 */
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{1, 25, 2, 0, 1}, /* RxD3 */
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{1, 26, 1, 0, 1}, /* RxER */
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{1, 28, 2, 0, 1}, /* Rx_DV */
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{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
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{1, 29, 2, 0, 1}, /* COL */
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{1, 31, 2, 0, 1}, /* CRS */
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{3, 4, 3, 0, 2}, /* MDIO */
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{3, 5, 1, 0, 2}, /* MDC */
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
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};
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int board_early_init_f(void)
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{
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volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
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/* Enable flash write */
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bcsr[9] &= ~0x08;
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_PQ_MDS_PIB
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pib_init();
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#endif
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return 0;
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}
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int fixed_sdram(void);
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int dram_init(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -ENXIO;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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msize = fixed_sdram();
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/* set total bus SDRAM size(bytes) -- DDR */
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gd->ram_size = msize * 1024 * 1024;
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return 0;
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}
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CONFIG_SYS_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1) {
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CONFIG_SYS_DDR_SIZE != 128)
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#warning Currenly any ddr size other than 128 is not supported
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#endif
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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__asm__ __volatile__ ("sync");
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udelay(200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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__asm__ __volatile__ ("sync");
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return msize;
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}
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int checkboard(void)
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{
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puts("Board: Freescale MPC832XEMDS\n");
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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