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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
255 lines
4.9 KiB
C
255 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_stream_id.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_sata.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <fsl_immap.h>
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#include <netdev.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <spl.h>
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#include <fsl_validate.h>
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#include "../common/sleep.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define DDR_SIZE 0x40000000
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int checkboard(void)
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{
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puts("Board: LS1021AIOT\n");
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#ifndef CONFIG_QSPI_BOOT
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struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 cpldrev;
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cpldrev = in_be32(&dcfg->gpporcr1);
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printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
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0xf));
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#endif
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return 0;
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}
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void ddrmc_init(void)
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{
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struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
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u32 temp_sdram_cfg, tmp;
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
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out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
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out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
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out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
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out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
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out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
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out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
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out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
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out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
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out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
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out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
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out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
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out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
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out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
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out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
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out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
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out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
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out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
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out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
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/* DDR erratum A-009942 */
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tmp = in_be32(&ddr->debug[28]);
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out_be32(&ddr->debug[28], tmp | 0x0070006f);
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udelay(500);
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temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
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}
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int dram_init(void)
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{
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#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
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ddrmc_init();
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#endif
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gd->ram_size = DDR_SIZE;
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[1] = {
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{CONFIG_SYS_FSL_ESDHC_ADDR},
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};
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int board_mmc_init(bd_t *bis)
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{
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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}
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#endif
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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if (is_serdes_configured(SGMII_TSEC1)) {
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puts("eTSEC1 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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if (is_serdes_configured(SGMII_TSEC2)) {
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puts("eTSEC2 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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#endif
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_TSEC_ENET
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/* clear BD & FR bits for BE BD's and frame data */
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clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
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#endif
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arch_soc_init();
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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/* Clear the BSS */
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memset(__bss_start, 0, __bss_end - __bss_start);
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get_clocks();
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preloader_console_init();
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dram_init();
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/* Allow OCRAM access permission as R/W */
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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board_init_r(NULL, 0);
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}
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#endif
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int board_init(void)
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{
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#ifndef CONFIG_SYS_FSL_NO_SERDES
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fsl_serdes_init();
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#endif
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ls102xa_smmu_stream_id_init();
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_SCSI_AHCI_PLAT
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ls1021a_sata_init();
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#endif
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return 0;
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}
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#endif
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#if defined(CONFIG_MISC_INIT_R)
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int misc_init_r(void)
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{
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#ifdef CONFIG_FSL_DEVICE_DISABLE
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device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
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#endif
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#ifdef CONFIG_FSL_CAAM
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return sec_init();
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#endif
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}
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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void flash_write16(u16 val, void *addr)
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{
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u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
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__raw_writew(shftval, addr);
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}
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u16 flash_read16(void *addr)
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{
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u16 val = __raw_readw(addr);
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
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}
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