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https://github.com/brain-hackers/u-boot-brain
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d1631fe1a0
This 2nd patch now removes all UIC mask bit definition. They should be generated from the vectors by using the UIC_MASK() macro from now on. This way only the vectors need to get defined for new PPC's. Also only the really used interrupt vectors are now defined. This makes definitions for new PPC versions easier and less error prone. Another part of this patch is that the 4xx emac driver got a little cleanup, since now the usage of the interrupts is clearer. Signed-off-by: Stefan Roese <sr@denx.de>
294 lines
8.8 KiB
C
294 lines
8.8 KiB
C
/*
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* (C) Copyright 2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PPC4xx_UIC_H_
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#define _PPC4xx_UIC_H_
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/*
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* Define the number of UIC's
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*/
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#if defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define UIC_MAX 4
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#elif defined(CONFIG_440GX) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_405EX)
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#define UIC_MAX 3
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#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
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defined(CONFIG_440EP) || defined(CONFIG_440GR)
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#define UIC_MAX 2
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#else
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#define UIC_MAX 1
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#endif
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/*
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* UIC register
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*/
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#define UIC_SR 0x0 /* UIC status */
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#define UIC_ER 0x2 /* UIC enable */
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#define UIC_CR 0x3 /* UIC critical */
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#define UIC_PR 0x4 /* UIC polarity */
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#define UIC_TR 0x5 /* UIC triggering */
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#define UIC_MSR 0x6 /* UIC masked status */
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#define UIC_VR 0x7 /* UIC vector */
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#define UIC_VCR 0x8 /* UIC vector configuration */
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#define UIC0_DCR_BASE 0xc0
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#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
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#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
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#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
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#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
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#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
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#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
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#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
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#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
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#define UIC1_DCR_BASE 0xd0
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#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
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#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
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#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
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#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
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#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
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#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
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#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
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#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
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#if defined(CONFIG_440GX)
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#define UIC2_DCR_BASE 0x210
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#else
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#define UIC2_DCR_BASE 0xe0
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#endif
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#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
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#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
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#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
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#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
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#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
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#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
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#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
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#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
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#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
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#define UIC3_DCR_BASE 0xf0
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#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
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#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
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#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
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#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
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#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
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#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
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#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
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#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
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#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
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#if defined(CONFIG_440GX)
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#define UIC_DCR_BASE 0x200
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#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
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#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
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#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
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#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
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#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
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#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
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#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
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#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration*/
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#endif /* CONFIG_440GX */
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/* The following is for compatibility with 405 code */
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#define uicsr uic0sr
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#define uicer uic0er
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#define uiccr uic0cr
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#define uicpr uic0pr
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#define uictr uic0tr
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#define uicmsr uic0msr
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#define uicvr uic0vr
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#define uicvcr uic0vcr
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/*
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* Now the interrupt vector definitions. They are different for most of
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* the 4xx variants, so we need some more #ifdef's here. No mask
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* definitions anymore here. For this please use the UIC_MASK macro below.
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*
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* Note: Please only define the interrupts really used in U-Boot here.
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* Those are the cascading and EMAC/MAL related interrupt.
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*/
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#if defined(CONFIG_405EP) || defined(CONFIG_405GP)
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#define VECNUM_MAL_SERR 10
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#define VECNUM_MAL_TXEOB 11
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#define VECNUM_MAL_RXEOB 12
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#define VECNUM_MAL_TXDE 13
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#define VECNUM_MAL_RXDE 14
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#define VECNUM_ETH0 15
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#define VECNUM_ETH1_OFFS 2
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#define VECNUM_EIRQ6 29
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#endif /* defined(CONFIG_405EP) */
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#if defined(CONFIG_405EZ)
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#define VECNUM_USBDEV 15
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#define VECNUM_ETH0 16
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#define VECNUM_MAL_SERR 18
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#define VECNUM_MAL_TXDE 18
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#define VECNUM_MAL_RXDE 18
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#define VECNUM_MAL_TXEOB 19
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#define VECNUM_MAL_RXEOB 21
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#endif /* CONFIG_405EX */
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#if defined(CONFIG_405EX)
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/* UIC 0 */
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#define VECNUM_MAL_TXEOB 10
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#define VECNUM_MAL_RXEOB 11
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#define VECNUM_ETH0 24
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#define VECNUM_ETH1_OFFS 1
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#define VECNUM_UIC2NCI 28
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#define VECNUM_UIC2CI 29
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#define VECNUM_UIC1NCI 30
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#define VECNUM_UIC1CI 31
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/* UIC 1 */
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#define VECNUM_MAL_SERR (32 + 0)
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#define VECNUM_MAL_TXDE (32 + 1)
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#define VECNUM_MAL_RXDE (32 + 2)
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#endif /* CONFIG_405EX */
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#if defined(CONFIG_440GP) || \
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defined(CONFIG_440EP) || defined(CONFIG_440GR)
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/* UIC 0 */
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#define VECNUM_MAL_TXEOB 10
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#define VECNUM_MAL_RXEOB 11
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#define VECNUM_UIC1NCI 30
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#define VECNUM_UIC1CI 31
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/* UIC 1 */
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#define VECNUM_MAL_SERR (32 + 0)
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#define VECNUM_MAL_TXDE (32 + 1)
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#define VECNUM_MAL_RXDE (32 + 2)
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#define VECNUM_USBDEV (32 + 23)
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#define VECNUM_ETH0 (32 + 28)
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#define VECNUM_ETH1_OFFS 2
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#endif /* CONFIG_440GP */
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#if defined(CONFIG_440GX)
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/* UIC 0 */
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#define VECNUM_MAL_TXEOB 10
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#define VECNUM_MAL_RXEOB 11
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/* UIC 1 */
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#define VECNUM_MAL_SERR (32 + 0)
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#define VECNUM_MAL_TXDE (32 + 1)
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#define VECNUM_MAL_RXDE (32 + 2)
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#define VECNUM_ETH0 (32 + 28)
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#define VECNUM_ETH1_OFFS 2
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/* UICB 0 (440GX only) */
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#define VECNUM_UIC0CI 0
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#define VECNUM_UIC0NCI 1
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#define VECNUM_UIC1CI 2
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#define VECNUM_UIC1NCI 3
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#define VECNUM_UIC2CI 4
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#define VECNUM_UIC2NCI 5
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#endif /* CONFIG_440GX */
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* UIC 0 */
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#define VECNUM_MAL_TXEOB 10
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#define VECNUM_MAL_RXEOB 11
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#define VECNUM_USBDEV 20
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#define VECNUM_ETH0 24
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#define VECNUM_ETH1_OFFS 1
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#define VECNUM_UIC2NCI 28
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#define VECNUM_UIC2CI 29
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#define VECNUM_UIC1NCI 30
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#define VECNUM_UIC1CI 31
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/* UIC 1 */
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#define VECNUM_MAL_SERR (32 + 0)
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#define VECNUM_MAL_TXDE (32 + 1)
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#define VECNUM_MAL_RXDE (32 + 2)
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/* UIC 2 */
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#define VECNUM_EIRQ2 (64 + 3)
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#endif /* CONFIG_440EPX */
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#if defined(CONFIG_440SP)
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/* UIC 0 */
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#define VECNUM_UIC1NCI 30
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#define VECNUM_UIC1CI 31
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/* UIC 1 */
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#define VECNUM_MAL_SERR (32 + 1)
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#define VECNUM_MAL_TXDE (32 + 2)
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#define VECNUM_MAL_RXDE (32 + 3)
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#define VECNUM_MAL_TXEOB (32 + 6)
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#define VECNUM_MAL_RXEOB (32 + 7)
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#define VECNUM_ETH0 (32 + 28)
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#endif /* CONFIG_440SP */
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#if defined(CONFIG_440SPE)
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/* UIC 0 */
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#define VECNUM_UIC2NCI 10
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#define VECNUM_UIC2CI 11
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#define VECNUM_UIC3NCI 16
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#define VECNUM_UIC3CI 17
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#define VECNUM_UIC1NCI 30
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#define VECNUM_UIC1CI 31
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/* UIC 1 */
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#define VECNUM_MAL_SERR (32 + 1)
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#define VECNUM_MAL_TXDE (32 + 2)
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#define VECNUM_MAL_RXDE (32 + 3)
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#define VECNUM_MAL_TXEOB (32 + 6)
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#define VECNUM_MAL_RXEOB (32 + 7)
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#define VECNUM_ETH0 (32 + 28)
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#endif /* CONFIG_440SPE */
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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/* UIC 0 */
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#define VECNUM_UIC2NCI 10
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#define VECNUM_UIC2CI 11
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#define VECNUM_UIC3NCI 16
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#define VECNUM_UIC3CI 17
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#define VECNUM_UIC1NCI 30
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#define VECNUM_UIC1CI 31
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/* UIC 2 */
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#define VECNUM_MAL_SERR (64 + 3)
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#define VECNUM_MAL_TXDE (64 + 4)
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#define VECNUM_MAL_RXDE (64 + 5)
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#define VECNUM_MAL_TXEOB (64 + 6)
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#define VECNUM_MAL_RXEOB (64 + 7)
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#define VECNUM_ETH0 (64 + 16)
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#define VECNUM_ETH1_OFFS 1
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#endif /* CONFIG_460EX */
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#if !defined(VECNUM_ETH1_OFFS)
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#define VECNUM_ETH1_OFFS 1
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#endif
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/*
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* Mask definitions (used for example in 4xx_enet.c)
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*/
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#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
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#define UIC_NR(vec) ((vec) >> 5)
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#endif /* _PPC4xx_UIC_H_ */
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