mirror of
https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
155 lines
3.8 KiB
C
155 lines
3.8 KiB
C
/*
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* (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Rockchip GMAC ethernet IP driver for U-Boot
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*/
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#include <common.h>
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#include <dm.h>
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#include <clk.h>
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#include <phy.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/grf_rk3288.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include "designware.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Platform data for the gmac
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*
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* dw_eth_pdata: Required platform data for designware driver (must be first)
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*/
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struct gmac_rockchip_platdata {
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struct dw_eth_pdata dw_eth_pdata;
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int tx_delay;
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int rx_delay;
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};
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static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
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{
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struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
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pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"tx-delay", 0x30);
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pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"rx-delay", 0x10);
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return designware_eth_ofdata_to_platdata(dev);
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}
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static int gmac_rockchip_fix_mac_speed(struct dw_eth_dev *priv)
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{
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struct rk3288_grf *grf;
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int clk;
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switch (priv->phydev->speed) {
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case 10:
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clk = GMAC_CLK_SEL_2_5M;
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break;
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case 100:
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clk = GMAC_CLK_SEL_25M;
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break;
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case 1000:
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clk = GMAC_CLK_SEL_125M;
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break;
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default:
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debug("Unknown phy speed: %d\n", priv->phydev->speed);
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return -EINVAL;
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}
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->soc_con1,
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GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT,
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clk << GMAC_CLK_SEL_SHIFT);
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return 0;
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}
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static int gmac_rockchip_probe(struct udevice *dev)
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{
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struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
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struct rk3288_grf *grf;
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struct clk clk;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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/* Since mac_clk is fed by an external clock we can use 0 here */
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ret = clk_set_rate(&clk, 0);
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if (ret)
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return ret;
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/* Set to RGMII mode */
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrsetreg(&grf->soc_con1,
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RMII_MODE_MASK << RMII_MODE_SHIFT |
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GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT,
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GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT);
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rk_clrsetreg(&grf->soc_con3,
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RXCLK_DLY_ENA_GMAC_MASK << RXCLK_DLY_ENA_GMAC_SHIFT |
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TXCLK_DLY_ENA_GMAC_MASK << TXCLK_DLY_ENA_GMAC_SHIFT |
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CLK_RX_DL_CFG_GMAC_MASK << CLK_RX_DL_CFG_GMAC_SHIFT |
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CLK_TX_DL_CFG_GMAC_MASK << CLK_TX_DL_CFG_GMAC_SHIFT,
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RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT |
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TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT |
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pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT |
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pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT);
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return designware_eth_probe(dev);
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}
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static int gmac_rockchip_eth_start(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct dw_eth_dev *priv = dev_get_priv(dev);
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int ret;
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ret = designware_eth_init(priv, pdata->enetaddr);
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if (ret)
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return ret;
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ret = gmac_rockchip_fix_mac_speed(priv);
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if (ret)
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return ret;
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ret = designware_eth_enable(priv);
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if (ret)
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return ret;
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return 0;
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}
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const struct eth_ops gmac_rockchip_eth_ops = {
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.start = gmac_rockchip_eth_start,
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.send = designware_eth_send,
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.recv = designware_eth_recv,
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.free_pkt = designware_eth_free_pkt,
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.stop = designware_eth_stop,
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.write_hwaddr = designware_eth_write_hwaddr,
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};
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static const struct udevice_id rockchip_gmac_ids[] = {
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{ .compatible = "rockchip,rk3288-gmac" },
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{ }
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};
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U_BOOT_DRIVER(eth_gmac_rockchip) = {
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.name = "gmac_rockchip",
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.id = UCLASS_ETH,
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.of_match = rockchip_gmac_ids,
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.ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
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.probe = gmac_rockchip_probe,
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.ops = &gmac_rockchip_eth_ops,
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.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
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.platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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