mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
e7dcf5645f
This header file is now only used by files that access internal environment features. Drop it from various places where it is not needed. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
363 lines
9.5 KiB
C
363 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* CI20 setup code
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*
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* Copyright (c) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <mach/jz4780.h>
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#include <mach/jz4780_dram.h>
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#include <mach/jz4780_gpio.h>
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struct ci20_otp {
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u32 serial_number;
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u32 date;
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u8 manufacturer[2];
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u8 mac[6];
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} __packed;
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static void ci20_mux_mmc(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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/* setup MSC1 pins */
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writel(0x30f00000, gpio_regs + GPIO_PXINTC(4));
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writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4));
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writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4));
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writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4));
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writel(0x30f00000, gpio_regs + GPIO_PXPENC(4));
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jz4780_clk_ungate_mmc();
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}
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#ifndef CONFIG_SPL_BUILD
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static void ci20_mux_eth(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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#ifdef CONFIG_NAND
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/* setup pins (some already setup for NAND) */
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writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
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writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
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writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0));
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writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0));
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writel(0x04030000, gpio_regs + GPIO_PXPENS(0));
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#else
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/* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
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writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0));
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writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0));
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writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0));
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writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0));
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writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0));
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writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
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writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
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writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
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writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
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writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
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#endif
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}
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static void ci20_mux_jtag(void)
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{
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#ifdef CONFIG_JTAG
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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/* enable JTAG */
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writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
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writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
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writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
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writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0));
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#endif
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}
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static void ci20_mux_nand(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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/* setup pins */
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writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0));
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writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0));
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writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0));
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writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0));
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writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0));
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writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
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writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
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writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
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writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
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writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
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/* FRB0_N */
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jz47xx_gpio_direction_input(JZ_GPIO(0, 20));
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writel(20, gpio_regs + GPIO_PXPENS(0));
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/* disable write protect */
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jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1);
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}
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static void ci20_mux_uart(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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/* UART0 */
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writel(0x9, gpio_regs + GPIO_PXINTC(5));
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writel(0x9, gpio_regs + GPIO_PXMASKC(5));
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writel(0x9, gpio_regs + GPIO_PXPAT1C(5));
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writel(0x9, gpio_regs + GPIO_PXPAT0C(5));
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writel(0x9, gpio_regs + GPIO_PXPENC(5));
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jz4780_clk_ungate_uart(0);
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/* UART 1 and 2 */
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jz4780_clk_ungate_uart(1);
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jz4780_clk_ungate_uart(2);
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#ifndef CONFIG_JTAG
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/* UART3 */
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writel(1 << 12, gpio_regs + GPIO_PXINTC(3));
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writel(1 << 12, gpio_regs + GPIO_PXMASKS(3));
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writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3));
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writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3));
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writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
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writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
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writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
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writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0));
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writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0));
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jz4780_clk_ungate_uart(3);
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#endif
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/* UART4 */
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writel(0x100400, gpio_regs + GPIO_PXINTC(2));
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writel(0x100400, gpio_regs + GPIO_PXMASKC(2));
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writel(0x100400, gpio_regs + GPIO_PXPAT1S(2));
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writel(0x100400, gpio_regs + GPIO_PXPAT0C(2));
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writel(0x100400, gpio_regs + GPIO_PXPENC(2));
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jz4780_clk_ungate_uart(4);
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}
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int board_early_init_f(void)
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{
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ci20_mux_jtag();
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ci20_mux_uart();
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ci20_mux_eth();
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ci20_mux_mmc();
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ci20_mux_nand();
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/* SYS_POWER_IND high (LED blue, VBUS off) */
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jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0);
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/* LEDs off */
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jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0);
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jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0);
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jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0);
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jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0);
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return 0;
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}
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int misc_init_r(void)
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{
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const u32 efuse_clk = jz4780_clk_get_efuse_clk();
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struct ci20_otp otp;
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char manufacturer[3];
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/* Read the board OTP data */
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jz4780_efuse_init(efuse_clk);
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jz4780_efuse_read(0x18, 16, (u8 *)&otp);
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/* Set MAC address */
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if (!is_valid_ethaddr(otp.mac)) {
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/* no MAC assigned, generate one from the unique chip ID */
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jz4780_efuse_read(0x8, 4, &otp.mac[0]);
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jz4780_efuse_read(0x12, 2, &otp.mac[4]);
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otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
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}
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eth_env_set_enetaddr("ethaddr", otp.mac);
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/* Put other board information into the environment */
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env_set_ulong("serial#", otp.serial_number);
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env_set_ulong("board_date", otp.date);
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manufacturer[0] = otp.manufacturer[0];
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manufacturer[1] = otp.manufacturer[1];
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manufacturer[2] = 0;
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env_set("board_mfr", manufacturer);
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return 0;
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}
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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/* Enable clock */
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jz4780_clk_ungate_ethernet();
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/* Enable power (PB25) */
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jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1);
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/* Reset (PF12) */
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mdelay(10);
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jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0);
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mdelay(10);
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jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1);
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mdelay(10);
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return dm9000_initialize(bis);
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}
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#endif /* CONFIG_DRIVER_DM9000 */
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#endif
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static u8 ci20_revision(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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int val;
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jz47xx_gpio_direction_input(JZ_GPIO(2, 18));
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jz47xx_gpio_direction_input(JZ_GPIO(2, 19));
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/* Enable pullups */
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writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2));
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/* Read PC18/19 for version */
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val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) |
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((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1);
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if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */
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return 1;
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if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */
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return 2;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = sdram_size(0) + sdram_size(1);
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return 0;
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}
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/* U-Boot common routines */
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int checkboard(void)
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{
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printf("Board: Creator CI20 (rev.%d)\n", ci20_revision());
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#if defined(CONFIG_SPL_MMC_SUPPORT)
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int board_mmc_init(bd_t *bd)
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{
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ci20_mux_mmc();
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return jz_mmc_init((void __iomem *)MSC0_BASE);
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}
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#endif
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static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
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.timing = {
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(4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
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(6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
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(4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) |
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(6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
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(4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
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(6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
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(21 << DDRC_TIMING3_TRC_BIT),
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(31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
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(4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) |
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(8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
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(8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
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(4 << DDRC_TIMING5_TWDLAT_BIT),
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(25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) |
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(2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
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},
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/* PHY */
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/* Mode Register 0 */
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.mr0 = 0x420,
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#ifdef SDRAM_DISABLE_DLL
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.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
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#else
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.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
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#endif
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.ptr0 = 0x002000d4,
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.ptr1 = 0x02230d40,
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.ptr2 = 0x04013880,
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.dtpr0 = 0x2a8f6690,
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.dtpr1 = 0x00400860,
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.dtpr2 = 0x10042a00,
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.pullup = 0x0b,
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.pulldn = 0x0b,
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};
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static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
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.timing = {
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(4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
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(6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
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(4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) |
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(6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
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(4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
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(6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
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(22 << DDRC_TIMING3_TRC_BIT),
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(42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
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(4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) |
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(3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
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(8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
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(4 << DDRC_TIMING5_TWDLAT_BIT),
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(25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) |
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(2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
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},
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/* PHY */
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/* Mode Register 0 */
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.mr0 = 0x420,
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#ifdef SDRAM_DISABLE_DLL
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.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
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#else
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.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
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#endif
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.ptr0 = 0x002000d4,
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.ptr1 = 0x02d30d40,
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.ptr2 = 0x04013880,
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.dtpr0 = 0x2c906690,
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.dtpr1 = 0x005608a0,
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.dtpr2 = 0x10042a00,
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.pullup = 0x0e,
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.pulldn = 0x0e,
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};
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#if (CONFIG_SYS_MHZ != 1200)
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#error No DDR configuration for CPU speed
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#endif
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const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
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{
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const int board_revision = ci20_revision();
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if (board_revision == 2)
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return &K4B2G0846Q_48_config;
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else /* Fall back to H5TQ2G83CFR RAM */
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return &H5TQ2G83CFR_48_config;
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}
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#endif
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