mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
699c4e592b
Initially IVT for ARCv2 was simply copypasted from ARCompact with some selected fixes so basic stuff works. Now we update it with more ARCv2 specific vectors like * Software Interrupt * Division by zero * Data cache consistency error * Misaligned access Also normal interrupts are now implemented properly and extened to all possible 240 items. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
180 lines
2.9 KiB
ArmAsm
180 lines
2.9 KiB
ArmAsm
/*
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* Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/linkage.h>
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/*
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* Note on the LD/ST addressing modes with address register write-back
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*
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* LD.a same as LD.aw
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*
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* LD.a reg1, [reg2, x] => Pre Incr
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* Eff Addr for load = [reg2 + x]
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*
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* LD.ab reg1, [reg2, x] => Post Incr
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* Eff Addr for load = [reg2]
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*/
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.macro PUSH reg
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st.a \reg, [%sp, -4]
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.endm
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.macro PUSHAX aux
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lr %r9, [\aux]
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PUSH %r9
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.endm
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.macro SAVE_R1_TO_R24
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PUSH %r1
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PUSH %r2
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PUSH %r3
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PUSH %r4
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PUSH %r5
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PUSH %r6
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PUSH %r7
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PUSH %r8
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PUSH %r9
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PUSH %r10
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PUSH %r11
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PUSH %r12
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PUSH %r13
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PUSH %r14
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PUSH %r15
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PUSH %r16
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PUSH %r17
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PUSH %r18
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PUSH %r19
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PUSH %r20
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PUSH %r21
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PUSH %r22
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PUSH %r23
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PUSH %r24
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.endm
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.macro SAVE_ALL_SYS
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/* saving %r0 to reg->r0 in advance since we read %ecr into it */
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st %r0, [%sp, -8]
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lr %r0, [%ecr] /* all stack addressing is manual so far */
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st %r0, [%sp]
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st %sp, [%sp, -4]
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/* now move %sp to reg->r0 position so we can do "push" automatically */
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sub %sp, %sp, 8
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SAVE_R1_TO_R24
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PUSH %r25
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PUSH %gp
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PUSH %fp
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PUSH %blink
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PUSHAX %eret
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PUSHAX %erstatus
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PUSH %lp_count
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PUSHAX %lp_end
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PUSHAX %lp_start
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PUSHAX %erbta
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.endm
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.macro SAVE_EXCEPTION_SOURCE
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#ifdef CONFIG_MMU
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/* If MMU exists exception faulting address is loaded in EFA reg */
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lr %r0, [%efa]
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#else
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/* Otherwise in ERET (exception return) reg */
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lr %r0, [%eret]
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#endif
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.endm
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ENTRY(memory_error)
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_memory_error
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ENDPROC(memory_error)
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ENTRY(instruction_error)
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_instruction_error
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ENDPROC(instruction_error)
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ENTRY(interrupt_handler)
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/* Todo - save and restore CPU context when interrupts will be in use */
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bl do_interrupt_handler
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rtie
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ENDPROC(interrupt_handler)
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ENTRY(EV_MachineCheck)
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_machine_check_fault
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ENDPROC(EV_MachineCheck)
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ENTRY(EV_TLBMissI)
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_itlb_miss
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ENDPROC(EV_TLBMissI)
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ENTRY(EV_TLBMissD)
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_dtlb_miss
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ENDPROC(EV_TLBMissD)
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ENTRY(EV_TLBProtV)
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_tlb_prot_violation
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ENDPROC(EV_TLBProtV)
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ENTRY(EV_PrivilegeV)
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_privilege_violation
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ENDPROC(EV_PrivilegeV)
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ENTRY(EV_Trap)
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_trap
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ENDPROC(EV_Trap)
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ENTRY(EV_Extension)
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_extension
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ENDPROC(EV_Extension)
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#ifdef CONFIG_ISA_ARCV2
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ENTRY(EV_SWI)
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_swi
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ENDPROC(EV_SWI)
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ENTRY(EV_DivZero)
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_divzero
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ENDPROC(EV_DivZero)
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ENTRY(EV_DCError)
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_dcerror
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ENDPROC(EV_DCError)
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ENTRY(EV_Maligned)
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_maligned
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ENDPROC(EV_Maligned)
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#endif
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