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https://github.com/brain-hackers/u-boot-brain
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ff9112df8b
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.
This will be the new structure:
drivers/ddr/marvell/axp
Supporting Armada XP (AXP) devices (and perhaps Armada 370)
drivers/ddr/marvell/a38x
Supporting Armada 38x devices (and perhaps Armada 39x)
Signed-off-by: Stefan Roese <sr@denx.de>
88 lines
2.4 KiB
C
88 lines
2.4 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __HIGHSPEED_ENV_SPEC_H
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#define __HIGHSPEED_ENV_SPEC_H
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#include "../../../drivers/ddr/marvell/axp/ddr3_hw_training.h"
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typedef enum {
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SERDES_UNIT_UNCONNECTED = 0x0,
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SERDES_UNIT_PEX = 0x1,
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SERDES_UNIT_SATA = 0x2,
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SERDES_UNIT_SGMII0 = 0x3,
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SERDES_UNIT_SGMII1 = 0x4,
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SERDES_UNIT_SGMII2 = 0x5,
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SERDES_UNIT_SGMII3 = 0x6,
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SERDES_UNIT_QSGMII = 0x7,
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SERDES_UNIT_SETM = 0x8,
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SERDES_LAST_UNIT
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} MV_BIN_SERDES_UNIT_INDX;
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typedef enum {
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PEX_BUS_DISABLED = 0,
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PEX_BUS_MODE_X1 = 1,
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PEX_BUS_MODE_X4 = 2,
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PEX_BUS_MODE_X8 = 3
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} MV_PEX_UNIT_CFG;
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typedef enum pex_type {
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MV_PEX_ROOT_COMPLEX, /* root complex device */
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MV_PEX_END_POINT /* end point device */
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} MV_PEX_TYPE;
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typedef struct serdes_change_m_phy {
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MV_BIN_SERDES_UNIT_INDX type;
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u32 reg_low_speed;
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u32 val_low_speed;
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u32 reg_hi_speed;
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u32 val_hi_speed;
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} MV_SERDES_CHANGE_M_PHY;
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/*
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* Configuration per SERDES line. Each nibble is MV_SERDES_LINE_TYPE
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*/
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typedef struct board_serdes_conf {
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MV_PEX_TYPE pex_type; /* MV_PEX_ROOT_COMPLEX MV_PEX_END_POINT */
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u32 line0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */
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u32 line8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */
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MV_PEX_UNIT_CFG pex_mode[4];
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/*
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* Bus speed - one bit per SERDES line:
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* Low speed (0) High speed (1)
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* PEX 2.5 G (10 bit) 5 G (20 bit)
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* SATA 1.5 G 3 G
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* SGMII 1.25 Gbps 3.125 Gbps
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*/
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u32 bus_speed;
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MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
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} MV_BIN_SERDES_CFG;
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#define BIN_SERDES_CFG { \
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{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
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{0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
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{0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
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{0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
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{0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
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{0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
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{0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
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{0, 1, -1 , 2, -1, -1, 3, -1, 4}, /* Lane 7*/ \
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{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 8 */ \
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{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 9 */ \
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{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 10 */ \
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{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 11 */ \
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{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 12 */ \
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{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 13 */ \
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{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 14 */ \
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{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 15 */ \
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}
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#endif /* __HIGHSPEED_ENV_SPEC_H */
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