mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 12:46:17 +09:00
b58385df3a
Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
40 lines
898 B
ArmAsm
40 lines
898 B
ArmAsm
/*
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* Copyright (C) 2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0
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* https://spdx.org/licenses
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*/
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#include <asm/arch-armada8k/cache_llc.h>
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#include <linux/linkage.h>
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/*
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* int __asm_flush_l3_dcache
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*
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* flush Armada-8K last level cache.
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*
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*/
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ENTRY(__asm_flush_l3_dcache)
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/* flush cache */
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mov x0, #LLC_BASE_ADDR
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add x0, x0, #LLC_FLUSH_BY_WAY
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movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
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mov w1, #LLC_WAY_MASK
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str w1, [x0]
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/* sync cache */
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mov x0, #LLC_BASE_ADDR
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add x0, x0, #LLC_CACHE_SYNC
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movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
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str wzr, [x0]
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/* check that cache sync completed */
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mov x0, #LLC_BASE_ADDR
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add x0, x0, #LLC_CACHE_SYNC_COMPLETE
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movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
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1: ldr w1, [x0]
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and w1, w1, #LLC_CACHE_SYNC_MASK
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cbnz w1, 1b
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/* return success */
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mov x0, #0
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ret
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ENDPROC(__asm_flush_l3_dcache)
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