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d133647af4
In addition to the current Android magic settings, allow to optionally use DDR3 timing parameters, which are tailored for different clock frequencies and JEDEC speed bins. This should improve reliability and performance. Adding '+S:CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H=y' to the board defconfig allows to use timings, which are calculated for the DDR3-1066F speed bin. A lot of DDR3 chips, which are used in real Allwinner based devices, support DDR3-1066F speed bin timings. And adding '+S:CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y' should work with any DDR3 chips, because this targets the slowest JEDEC speed bins. The vendor magic values are still used by default for DRAM, but board maintainers now have more flexibility in DRAM timings selection. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
36 lines
627 B
C
36 lines
627 B
C
/* DRAM parameters for auto dram configuration on sun5i and sun7i */
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#include <common.h>
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#include <asm/arch/dram.h>
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static struct dram_para dram_para = {
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.clock = CONFIG_DRAM_CLK,
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.type = 3,
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.rank_num = 1,
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.density = 0,
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.io_width = 0,
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.bus_width = 0,
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.zq = CONFIG_DRAM_ZQ,
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.odt_en = 0,
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.size = 0,
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#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
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.cas = 9,
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.tpr0 = 0x42d899b7,
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.tpr1 = 0xa090,
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.tpr2 = 0x22a00,
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.emr2 = 0x10,
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#else
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# include "dram_timings_sun4i.h"
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#endif
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.tpr3 = 0,
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.tpr4 = 0,
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.tpr5 = 0,
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.emr1 = CONFIG_DRAM_EMR1,
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.emr3 = 0,
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};
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unsigned long sunxi_dram_init(void)
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{
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return dramc_init(&dram_para);
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}
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