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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
273 lines
5.7 KiB
C
273 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <hang.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <altera.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <watchdog.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/nic301.h>
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#include <asm/arch/scu.h>
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#include <asm/pl310.h>
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DECLARE_GLOBAL_DATA_PTR;
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phys_addr_t socfpga_clkmgr_base __section(".data");
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phys_addr_t socfpga_rstmgr_base __section(".data");
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phys_addr_t socfpga_sysmgr_base __section(".data");
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#ifdef CONFIG_SYS_L2_PL310
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static const struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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#endif
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struct bsel bsel_str[] = {
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{ "rsvd", "Reserved", },
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{ "fpga", "FPGA (HPS2FPGA Bridge)", },
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{ "nand", "NAND Flash (1.8V)", },
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{ "nand", "NAND Flash (3.0V)", },
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{ "sd", "SD/MMC External Transceiver (1.8V)", },
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{ "sd", "SD/MMC Internal Transceiver (3.0V)", },
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{ "qspi", "QSPI Flash (1.8V)", },
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{ "qspi", "QSPI Flash (3.0V)", },
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};
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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void enable_caches(void)
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{
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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icache_enable();
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#endif
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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dcache_enable();
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#endif
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}
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#ifdef CONFIG_SYS_L2_PL310
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void v7_outer_cache_enable(void)
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{
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struct udevice *dev;
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if (uclass_get_device(UCLASS_CACHE, 0, &dev))
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pr_err("cache controller driver NOT found!\n");
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}
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void v7_outer_cache_disable(void)
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{
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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void socfpga_pl310_clear(void)
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{
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u32 mask = 0xff, ena = 0;
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icache_enable();
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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writel(0x0, &pl310->pl310_tag_latency_ctrl);
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writel(0x10, &pl310->pl310_data_latency_ctrl);
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/* enable BRESP, instruction and data prefetch, full line of zeroes */
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setbits_le32(&pl310->pl310_aux_ctrl,
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L310_AUX_CTRL_DATA_PREFETCH_MASK |
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L310_AUX_CTRL_INST_PREFETCH_MASK |
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L310_SHARED_ATT_OVERRIDE_ENABLE);
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/* Enable the L2 cache */
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ena = readl(&pl310->pl310_ctrl);
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ena |= L2X0_CTRL_EN;
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/*
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* Invalidate the PL310 L2 cache. Keep the invalidation code
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* entirely in L1 I-cache to avoid any bus traffic through
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* the L2.
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*/
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asm volatile(
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".align 5 \n"
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" b 3f \n"
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"1: str %1, [%4] \n"
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" dsb \n"
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" isb \n"
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" str %0, [%2] \n"
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" dsb \n"
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" isb \n"
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"2: ldr %0, [%2] \n"
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" cmp %0, #0 \n"
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" bne 2b \n"
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" str %0, [%3] \n"
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" dsb \n"
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" isb \n"
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" b 4f \n"
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"3: b 1b \n"
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"4: nop \n"
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: "+r"(mask), "+r"(ena)
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: "r"(&pl310->pl310_inv_way),
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"r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
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: "memory", "cc");
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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#endif
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#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
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defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
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int overwrite_console(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_FPGA
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/* add device descriptor to FPGA device table */
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void socfpga_fpga_add(void *fpga_desc)
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{
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fpga_init();
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fpga_add(fpga_altera, fpga_desc);
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}
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#endif
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int arch_cpu_init(void)
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{
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socfpga_get_managers_addr();
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#ifdef CONFIG_HW_WATCHDOG
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/*
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* In case the watchdog is enabled, make sure to (re-)configure it
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* so that the defined timeout is valid. Otherwise the SPL (Perloader)
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* timeout value is still active which might too short for Linux
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* booting.
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*/
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hw_watchdog_init();
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#else
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/*
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* If the HW watchdog is NOT enabled, make sure it is not running,
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* for example because it was enabled in the preloader. This might
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* trigger a watchdog-triggered reboot of Linux kernel later.
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* Toggle watchdog reset, so watchdog in not running state.
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*/
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
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#endif
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned int mask = ~0;
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if (argc < 2 || argc > 3)
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return CMD_RET_USAGE;
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argv++;
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if (argc == 3)
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mask = simple_strtoul(argv[1], NULL, 16);
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switch (*argv[0]) {
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case 'e': /* Enable */
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do_bridge_reset(1, mask);
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break;
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case 'd': /* Disable */
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do_bridge_reset(0, mask);
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break;
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default:
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return CMD_RET_USAGE;
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}
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return 0;
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}
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U_BOOT_CMD(bridge, 3, 1, do_bridge,
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"SoCFPGA HPS FPGA bridge control",
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"enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
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"bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
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""
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);
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#endif
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static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
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{
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const void *blob = gd->fdt_blob;
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struct fdt_resource r;
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int node;
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int ret;
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node = fdt_node_offset_by_compatible(blob, -1, compat);
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if (node < 0)
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return node;
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if (!fdtdec_get_is_enabled(blob, node))
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return -ENODEV;
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ret = fdt_get_resource(blob, node, "reg", 0, &r);
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if (ret)
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return ret;
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*base = (phys_addr_t)r.start;
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return 0;
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}
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void socfpga_get_managers_addr(void)
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{
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int ret;
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ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
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if (ret)
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hang();
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ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
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if (ret)
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hang();
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#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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ret = socfpga_get_base_addr("intel,agilex-clkmgr",
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&socfpga_clkmgr_base);
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#else
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ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
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#endif
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if (ret)
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hang();
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}
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phys_addr_t socfpga_get_rstmgr_addr(void)
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{
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return socfpga_rstmgr_base;
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}
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phys_addr_t socfpga_get_sysmgr_addr(void)
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{
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return socfpga_sysmgr_base;
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}
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phys_addr_t socfpga_get_clkmgr_addr(void)
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{
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return socfpga_clkmgr_base;
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}
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