mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-09 03:33:45 +09:00
12bbc0ba81
If without switch to main crystal oscillator, the sama5d3 SoC will use internal on chip RC oscillator. In order to get better accuracy, switch to main crystal oscillator. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
134 lines
2.6 KiB
C
134 lines
2.6 KiB
C
/*
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* Copyright (C) 2013 Atmel Corporation
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* Bo Shen <voice.shen@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_wdt.h>
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#include <asm/arch/clk.h>
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#include <spl.h>
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static void at91_disable_wdt(void)
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{
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struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
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writel(AT91_WDT_MR_WDDIS, &wdt->mr);
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}
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static void switch_to_main_crystal_osc(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 tmp;
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tmp = readl(&pmc->mor);
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tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff);
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tmp &= ~AT91_PMC_MOR_KEY(0xff);
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tmp |= AT91_PMC_MOR_MOSCEN;
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tmp |= AT91_PMC_MOR_OSCOUNT(8);
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tmp |= AT91_PMC_MOR_KEY(0x37);
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writel(tmp, &pmc->mor);
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while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS))
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;
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tmp = readl(&pmc->mor);
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tmp &= ~AT91_PMC_MOR_OSCBYPASS;
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tmp &= ~AT91_PMC_MOR_KEY(0xff);
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tmp |= AT91_PMC_MOR_KEY(0x37);
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writel(tmp, &pmc->mor);
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tmp = readl(&pmc->mor);
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tmp |= AT91_PMC_MOR_MOSCSEL;
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tmp &= ~AT91_PMC_MOR_KEY(0xff);
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tmp |= AT91_PMC_MOR_KEY(0x37);
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writel(tmp, &pmc->mor);
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while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS))
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;
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tmp = readl(&pmc->mor);
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tmp &= ~AT91_PMC_MOR_MOSCRCEN;
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tmp &= ~AT91_PMC_MOR_KEY(0xff);
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tmp |= AT91_PMC_MOR_KEY(0x37);
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writel(tmp, &pmc->mor);
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}
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void at91_plla_init(u32 pllar)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(pllar, &pmc->pllar);
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while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
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;
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}
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void at91_mck_init(u32 mckr)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 tmp;
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tmp = readl(&pmc->mckr);
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tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
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AT91_PMC_MCKR_MDIV_MASK |
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AT91_PMC_MCKR_PLLADIV_2);
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tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
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AT91_PMC_MCKR_MDIV_MASK |
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AT91_PMC_MCKR_PLLADIV_2);
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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}
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u32 spl_boot_device(void)
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{
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#ifdef CONFIG_SYS_USE_MMC
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return BOOT_DEVICE_MMC1;
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#elif CONFIG_SYS_USE_NANDFLASH
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return BOOT_DEVICE_NAND;
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#elif CONFIG_SYS_USE_SERIALFLASH
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return BOOT_DEVICE_SPI;
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#endif
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return BOOT_DEVICE_NONE;
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}
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u32 spl_boot_mode(void)
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{
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switch (spl_boot_device()) {
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#ifdef CONFIG_SYS_USE_MMC
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case BOOT_DEVICE_MMC1:
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return MMCSD_MODE_FAT;
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break;
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#endif
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case BOOT_DEVICE_NONE:
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default:
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hang();
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}
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}
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void s_init(void)
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{
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switch_to_main_crystal_osc();
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/* disable watchdog */
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at91_disable_wdt();
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/* PMC configuration */
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at91_pmc_init();
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at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
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timer_init();
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board_early_init_f();
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preloader_console_init();
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mem_init();
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}
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