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https://github.com/brain-hackers/u-boot-brain
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3eda55a32d
r8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we need to enable SMP bit of Auxiliary Control Register. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
90 lines
1.7 KiB
ArmAsm
90 lines
1.7 KiB
ArmAsm
/*
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* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
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* This file is lager low level initialize.
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*
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* Copyright (C) 2013, 2014 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <config.h>
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#include <linux/linkage.h>
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ENTRY(lowlevel_init)
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mrc p15, 0, r4, c0, c0, 5 /* mpidr */
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orr r4, r4, r4, lsr #6
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and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
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b do_lowlevel_init
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.pool
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/*
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* CPU ID #1-#3 come here
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*/
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.align 4
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do_cpu_waiting:
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ldr r1, =0xe6180000 /* sysc */
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1: ldr r0, [r1, #0x20] /* sbar */
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tst r0, r0
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beq 1b
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bx r0
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/*
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* Only CPU ID #0 comes here
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*/
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.align 4
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do_lowlevel_init:
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ldr r2, =0xFF000044 /* PRR */
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ldr r1, [r2]
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and r1, r1, #0x7F00
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lsrs r1, r1, #8
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cmp r1, #0x4C /* 0x4C is ID of r8a7794 */
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beq _enable_actlr_smp
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/* surpress wfe if ca15 */
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tst r4, #4
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mrceq p15, 0, r0, c1, c0, 1 /* actlr */
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orreq r0, r0, #(1<<7)
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mcreq p15, 0, r0, c1, c0, 1
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/* and set l2 latency */
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mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
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and r0, r0, #0xf00
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lsr r0, r0, #8
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tst r0, #1 /* only need for cluster 0 */
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bne _exit_init_l2_a15
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mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
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and r1, r0, #7
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cmp r1, #3 /* has already been set up */
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bicne r0, r0, #0xe7
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orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
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#if defined(CONFIG_R8A7790)
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orrne r0, r0, #0x20 /* L2CTLR[5] */
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#endif
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mcrne p15, 1, r0, c9, c0, 2
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b _exit_init_l2_a15
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_enable_actlr_smp: /* R8A7794 only (CA7) */
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#ifndef CONFIG_DCACHE_OFF
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #0x40
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mcr p15, 0, r0, c1, c0, 1
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#endif
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_exit_init_l2_a15:
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ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
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sub sp, r3, #4
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str lr, [sp]
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/* initialize system */
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bl s_init
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ldr lr, [sp]
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mov pc, lr
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nop
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ENDPROC(lowlevel_init)
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.ltorg
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