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https://github.com/brain-hackers/u-boot-brain
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![Jagan Teki](/assets/img/avatar_default.png)
Masking clock gate, reset register bits based on the probed controller is proper only due to the assumption that masking should start with 0 even thought the controller has separate PHY or shared between OTG. unfortunately these are fixed due to lack of separate clock, reset drivers. Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) so we need to start reg_mask 0 - 2. This patch calculated the mask, based on the register base so that we can get the proper bits to set with respect to probed controller. We even do this masking by using PHY index specifier from dt, but dev_read_addr_size is failing for 64-bit boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
205 lines
4.8 KiB
C
205 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Sunxi ehci glue
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*
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* Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <dm.h>
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#include "ehci.h"
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#include <generic-phy.h>
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#ifdef CONFIG_SUNXI_GEN_SUN4I
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#define BASE_DIST 0x8000
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#define AHB_CLK_DIST 2
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#else
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#define BASE_DIST 0x1000
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#define AHB_CLK_DIST 1
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#endif
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#define SUN6I_AHB_RESET0_CFG_OFFSET 0x2c0
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#define SUN9I_AHB_RESET0_CFG_OFFSET 0x5a0
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struct ehci_sunxi_cfg {
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bool has_reset;
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u32 extra_ahb_gate_mask;
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u32 reset0_cfg_offset;
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};
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struct ehci_sunxi_priv {
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struct ehci_ctrl ehci;
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struct sunxi_ccm_reg *ccm;
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u32 *reset0_cfg;
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int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
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struct phy phy;
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const struct ehci_sunxi_cfg *cfg;
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};
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static int ehci_usb_probe(struct udevice *dev)
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{
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struct usb_platdata *plat = dev_get_platdata(dev);
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struct ehci_sunxi_priv *priv = dev_get_priv(dev);
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struct ehci_hccr *hccr = (struct ehci_hccr *)devfdt_get_addr(dev);
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struct ehci_hcor *hcor;
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int extra_ahb_gate_mask = 0;
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u8 reg_mask = 0;
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int phys, ret;
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priv->cfg = (const struct ehci_sunxi_cfg *)dev_get_driver_data(dev);
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priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (IS_ERR(priv->ccm))
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return PTR_ERR(priv->ccm);
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priv->reset0_cfg = (void *)priv->ccm +
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priv->cfg->reset0_cfg_offset;
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phys = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
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if (phys < 0) {
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phys = 0;
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goto no_phy;
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}
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ret = generic_phy_get_by_name(dev, "usb", &priv->phy);
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if (ret) {
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pr_err("failed to get %s usb PHY\n", dev->name);
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return ret;
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}
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ret = generic_phy_init(&priv->phy);
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if (ret) {
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pr_err("failed to init %s USB PHY\n", dev->name);
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return ret;
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}
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ret = generic_phy_power_on(&priv->phy);
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if (ret) {
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pr_err("failed to power on %s USB PHY\n", dev->name);
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return ret;
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}
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no_phy:
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/*
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* This should go away once we've moved to the driver model for
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* clocks resp. phys.
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*/
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reg_mask = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
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priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
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extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask;
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priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST;
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extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST;
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setbits_le32(&priv->ccm->ahb_gate0,
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priv->ahb_gate_mask | extra_ahb_gate_mask);
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if (priv->cfg->has_reset)
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setbits_le32(priv->reset0_cfg,
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priv->ahb_gate_mask | extra_ahb_gate_mask);
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hcor = (struct ehci_hcor *)((uintptr_t)hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type);
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}
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static int ehci_usb_remove(struct udevice *dev)
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{
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struct ehci_sunxi_priv *priv = dev_get_priv(dev);
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int ret;
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if (generic_phy_valid(&priv->phy)) {
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ret = generic_phy_exit(&priv->phy);
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if (ret) {
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pr_err("failed to exit %s USB PHY\n", dev->name);
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return ret;
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}
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}
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ret = ehci_deregister(dev);
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if (ret)
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return ret;
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if (priv->cfg->has_reset)
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clrbits_le32(priv->reset0_cfg, priv->ahb_gate_mask);
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clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask);
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return 0;
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}
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static const struct ehci_sunxi_cfg sun4i_a10_cfg = {
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.has_reset = false,
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};
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static const struct ehci_sunxi_cfg sun6i_a31_cfg = {
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.has_reset = true,
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.reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET,
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};
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static const struct ehci_sunxi_cfg sun8i_h3_cfg = {
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.has_reset = true,
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.extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0,
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.reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET,
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};
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static const struct ehci_sunxi_cfg sun9i_a80_cfg = {
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.has_reset = true,
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.reset0_cfg_offset = SUN9I_AHB_RESET0_CFG_OFFSET,
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};
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static const struct udevice_id ehci_usb_ids[] = {
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{
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.compatible = "allwinner,sun4i-a10-ehci",
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.data = (ulong)&sun4i_a10_cfg,
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},
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{
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.compatible = "allwinner,sun5i-a13-ehci",
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.data = (ulong)&sun4i_a10_cfg,
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},
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{
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.compatible = "allwinner,sun6i-a31-ehci",
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.data = (ulong)&sun6i_a31_cfg,
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},
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{
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.compatible = "allwinner,sun7i-a20-ehci",
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.data = (ulong)&sun4i_a10_cfg,
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},
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{
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.compatible = "allwinner,sun8i-a23-ehci",
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.data = (ulong)&sun6i_a31_cfg,
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},
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{
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.compatible = "allwinner,sun8i-a83t-ehci",
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.data = (ulong)&sun6i_a31_cfg,
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},
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{
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.compatible = "allwinner,sun8i-h3-ehci",
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.data = (ulong)&sun8i_h3_cfg,
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},
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{
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.compatible = "allwinner,sun9i-a80-ehci",
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.data = (ulong)&sun9i_a80_cfg,
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},
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{
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.compatible = "allwinner,sun50i-a64-ehci",
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.data = (ulong)&sun8i_h3_cfg,
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},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(ehci_sunxi) = {
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.name = "ehci_sunxi",
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.id = UCLASS_USB,
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.of_match = ehci_usb_ids,
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.probe = ehci_usb_probe,
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.remove = ehci_usb_remove,
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.ops = &ehci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct ehci_sunxi_priv),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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