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https://github.com/brain-hackers/u-boot-brain
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61f66fd5a8
This patch reads EFUSE_BOOTROM register to see the maximum supported clock for CORE and TETRIS PLLs and configure them accordingly. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
55 lines
967 B
C
55 lines
967 B
C
/*
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* K2E EVM : Board initialization
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/ddr3.h>
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#include <asm/arch/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int external_clk[ext_clk_count] = {
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[sys_clk] = 100000000,
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[alt_core_clk] = 100000000,
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[pa_clk] = 100000000,
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[ddr3_clk] = 100000000,
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[mcm_clk] = 312500000,
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[pcie_clk] = 100000000,
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[sgmii_clk] = 156250000,
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[xgmii_clk] = 156250000,
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[usb_clk] = 100000000,
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};
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static struct pll_init_data core_pll_config[] = {
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CORE_PLL_800,
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CORE_PLL_850,
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CORE_PLL_1000,
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CORE_PLL_1250,
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CORE_PLL_1350,
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CORE_PLL_1400,
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CORE_PLL_1500,
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};
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static struct pll_init_data pa_pll_config =
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PASS_PLL_1000;
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#if defined(CONFIG_BOARD_EARLY_INIT_F)
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int board_early_init_f(void)
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{
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int speed;
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speed = get_max_dev_speed();
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init_pll(&core_pll_config[speed]);
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init_pll(&pa_pll_config);
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return 0;
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}
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#endif
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