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https://github.com/brain-hackers/u-boot-brain
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77b0e2239a
In case the MX23/MX28 is switched into JTAG mode via the BootMode select switches, the BootROM bypasses the CPU core registers initialization. This in turn means that the Stack Pointer (SP) register is not set as it is in every other mode of operation, but instead is only zeroed out. To prevent U-Boot SPL from crashing in this obscure JTAG mode, configure the SP to point at the CONFIG_SYS_INIT_SP_ADDR if the SP is zeroed out. Note that in case the SP is already configured, we must preserve that exact SP value and must not modify it. This is important since in every other mode but the JTAG mode, the SPL returns into the BootROM and BootROM in turn loads U-Boot itself. If the SP were to be corrupted, the BootROM won't be able to continue it's operation after returned from SPL and the system would crash. Finally, add the JTAG mode switch identifier, so it's not recognised as Unknown mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
/*
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* Freescale i.MX23/i.MX28 specific functions
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SYS_PROTO_H__
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#define __SYS_PROTO_H__
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int mxs_reset_block(struct mxs_register_32 *reg);
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int mxs_wait_mask_set(struct mxs_register_32 *reg,
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uint32_t mask,
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unsigned int timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg,
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uint32_t mask,
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unsigned int timeout);
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int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
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#ifdef CONFIG_SPL_BUILD
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#if defined(CONFIG_MX23)
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#include <asm/arch/iomux-mx23.h>
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#elif defined(CONFIG_MX28)
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#include <asm/arch/iomux-mx28.h>
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#endif
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void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
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const iomux_cfg_t *iomux_setup,
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const unsigned int iomux_size);
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#endif
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struct mxs_pair {
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uint8_t boot_pads;
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uint8_t boot_mask;
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const char *mode;
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};
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static const struct mxs_pair mxs_boot_modes[] = {
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#if defined(CONFIG_MX23)
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{ 0x00, 0x0f, "USB" },
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{ 0x01, 0x1f, "I2C, master" },
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{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
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{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
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{ 0x04, 0x1f, "NAND" },
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{ 0x06, 0x1f, "JTAG" },
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{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
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{ 0x09, 0x1f, "SSP SD/MMC #0" },
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{ 0x0a, 0x1f, "SSP SD/MMC #1" },
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{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
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#elif defined(CONFIG_MX28)
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{ 0x00, 0x0f, "USB #0" },
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{ 0x01, 0x1f, "I2C #0, master, 3V3" },
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{ 0x11, 0x1f, "I2C #0, master, 1V8" },
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{ 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
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{ 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
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{ 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
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{ 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
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{ 0x04, 0x1f, "NAND, 3V3" },
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{ 0x14, 0x1f, "NAND, 1V8" },
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{ 0x06, 0x1f, "JTAG" },
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{ 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
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{ 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
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{ 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
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{ 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
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{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
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{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
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{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
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#endif
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};
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struct mxs_spl_data {
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uint8_t boot_mode_idx;
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uint32_t mem_dram_size;
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};
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int mxs_dram_init(void);
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#endif /* __SYS_PROTO_H__ */
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